gem5/cpu/beta_cpu/rename_map.hh
Kevin Lim 5c4714c1a9 Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes.
SConscript:
    Include new files.
arch/alpha/isa_desc:
    Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them.
arch/alpha/isa_traits.hh:
    Add enum for total number of data registers.
arch/isa_parser.py:
base/traceflags.py:
    Include new light-weight OoO CPU model.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
    Changes to abstract more away from the base dyn inst class.
cpu/beta_cpu/2bit_local_pred.cc:
cpu/beta_cpu/2bit_local_pred.hh:
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
    Remove redundant SatCounter class.
cpu/beta_cpu/alpha_dyn_inst.cc:
cpu/beta_cpu/alpha_full_cpu.cc:
cpu/beta_cpu/alpha_full_cpu.hh:
cpu/beta_cpu/bpred_unit.cc:
cpu/beta_cpu/inst_queue.cc:
cpu/beta_cpu/mem_dep_unit.cc:
cpu/beta_cpu/ras.cc:
cpu/beta_cpu/rename_map.cc:
cpu/beta_cpu/rename_map.hh:
cpu/beta_cpu/rob.cc:
    Fix for gcc-3.4
cpu/beta_cpu/alpha_dyn_inst.hh:
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Fixes for gcc-3.4.
    Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Make params match the current params inherited from BaseCPU.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Fixes for gcc-3.4
cpu/beta_cpu/full_cpu.cc:
    Use new params pointer in BaseCPU.
    Fix for gcc-3.4.
cpu/beta_cpu/full_cpu.hh:
    Use new params class from BaseCPU.
cpu/beta_cpu/iew_impl.hh:
    Remove unused function.
cpu/simple_cpu/simple_cpu.cc:
    Remove unused global variable.
cpu/static_inst.hh:
    Include OoODynInst for new lightweight OoO CPU

--HG--
extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
2005-02-25 18:00:49 -05:00

142 lines
4 KiB
C++

// Todo: Create destructor.
// Have it so that there's a more meaningful name given to the variable
// that marks the beginning of the FP registers.
#ifndef __CPU_BETA_CPU_RENAME_MAP_HH__
#define __CPU_BETA_CPU_RENAME_MAP_HH__
#include <iostream>
#include <utility>
#include <vector>
#include "cpu/beta_cpu/free_list.hh"
class SimpleRenameMap
{
public:
/**
* Pair of a logical register and a physical register. Tells the
* previous mapping of a logical register to a physical register.
* Used to roll back the rename map to a previous state.
*/
typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo;
/**
* Pair of a physical register and a physical register. Used to
* return the physical register that a logical register has been
* renamed to, and the previous physical register that the same
* logical register was previously mapped to.
*/
typedef std::pair<PhysRegIndex, PhysRegIndex> RenameInfo;
public:
//Constructor
SimpleRenameMap(unsigned _numLogicalIntRegs,
unsigned _numPhysicalIntRegs,
unsigned _numLogicalFloatRegs,
unsigned _numPhysicalFloatRegs,
unsigned _numMiscRegs,
RegIndex _intZeroReg,
RegIndex _floatZeroReg);
/** Destructor. */
~SimpleRenameMap();
void setFreeList(SimpleFreeList *fl_ptr);
//Tell rename map to get a free physical register for a given
//architected register. Not sure it should have a return value,
//but perhaps it should have some sort of fault in case there are
//no free registers.
RenameInfo rename(RegIndex arch_reg);
PhysRegIndex lookup(RegIndex phys_reg);
bool isReady(PhysRegIndex arch_reg);
/**
* Marks the given register as ready, meaning that its value has been
* calculated and written to the register file.
* @params ready_reg The index of the physical register that is now
* ready.
*/
void markAsReady(PhysRegIndex ready_reg);
void setEntry(RegIndex arch_reg, PhysRegIndex renamed_reg);
void squash(std::vector<RegIndex> freed_regs,
std::vector<UnmapInfo> unmaps);
int numFreeEntries();
private:
/** Number of logical integer registers. */
int numLogicalIntRegs;
/** Number of physical integer registers. */
int numPhysicalIntRegs;
/** Number of logical floating point registers. */
int numLogicalFloatRegs;
/** Number of physical floating point registers. */
int numPhysicalFloatRegs;
/** Number of miscellaneous registers. */
int numMiscRegs;
/** Number of logical integer + float registers. */
int numLogicalRegs;
/** Number of physical integer + float registers. */
int numPhysicalRegs;
/** The integer zero register. This implementation assumes it is always
* zero and never can be anything else.
*/
RegIndex intZeroReg;
/** The floating point zero register. This implementation assumes it is
* always zero and never can be anything else.
*/
RegIndex floatZeroReg;
class RenameEntry
{
public:
PhysRegIndex physical_reg;
bool valid;
RenameEntry()
: physical_reg(0), valid(false)
{ }
};
/** Integer rename map. */
RenameEntry *intRenameMap;
/** Floating point rename map. */
RenameEntry *floatRenameMap;
/** Free list interface. */
SimpleFreeList *freeList;
// Might want to make all these scoreboards into one large scoreboard.
/** Scoreboard of physical integer registers, saying whether or not they
* are ready.
*/
std::vector<bool> intScoreboard;
/** Scoreboard of physical floating registers, saying whether or not they
* are ready.
*/
std::vector<bool> floatScoreboard;
/** Scoreboard of miscellaneous registers, saying whether or not they
* are ready.
*/
std::vector<bool> miscScoreboard;
};
#endif //__CPU_BETA_CPU_RENAME_MAP_HH__