SConscript: Include new files. arch/alpha/isa_desc: Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them. arch/alpha/isa_traits.hh: Add enum for total number of data registers. arch/isa_parser.py: base/traceflags.py: Include new light-weight OoO CPU model. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Changes to abstract more away from the base dyn inst class. cpu/beta_cpu/2bit_local_pred.cc: cpu/beta_cpu/2bit_local_pred.hh: cpu/beta_cpu/tournament_pred.cc: cpu/beta_cpu/tournament_pred.hh: Remove redundant SatCounter class. cpu/beta_cpu/alpha_dyn_inst.cc: cpu/beta_cpu/alpha_full_cpu.cc: cpu/beta_cpu/alpha_full_cpu.hh: cpu/beta_cpu/bpred_unit.cc: cpu/beta_cpu/inst_queue.cc: cpu/beta_cpu/mem_dep_unit.cc: cpu/beta_cpu/ras.cc: cpu/beta_cpu/rename_map.cc: cpu/beta_cpu/rename_map.hh: cpu/beta_cpu/rob.cc: Fix for gcc-3.4 cpu/beta_cpu/alpha_dyn_inst.hh: cpu/beta_cpu/alpha_dyn_inst_impl.hh: Fixes for gcc-3.4. Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst. cpu/beta_cpu/alpha_full_cpu_builder.cc: Make params match the current params inherited from BaseCPU. cpu/beta_cpu/alpha_full_cpu_impl.hh: Fixes for gcc-3.4 cpu/beta_cpu/full_cpu.cc: Use new params pointer in BaseCPU. Fix for gcc-3.4. cpu/beta_cpu/full_cpu.hh: Use new params class from BaseCPU. cpu/beta_cpu/iew_impl.hh: Remove unused function. cpu/simple_cpu/simple_cpu.cc: Remove unused global variable. cpu/static_inst.hh: Include OoODynInst for new lightweight OoO CPU --HG-- extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
322 lines
8.6 KiB
C++
322 lines
8.6 KiB
C++
//Todo: Add in a lot of the functions that are ISA specific. Also define
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//the functions that currently exist within the base cpu class. Define
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//everything for the simobject stuff so it can be serialized and
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//instantiated, add in debugging statements everywhere. Have CPU schedule
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//itself properly. Constructor. Derived alpha class. Threads!
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// Avoid running stages and advancing queues if idle/stalled.
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#ifndef __SIMPLE_FULL_CPU_HH__
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#define __SIMPLE_FULL_CPU_HH__
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#include <iostream>
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#include <list>
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#include "cpu/beta_cpu/comm.hh"
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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#include "cpu/base_cpu.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/beta_cpu/cpu_policy.hh"
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#include "sim/process.hh"
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class FunctionalMemory;
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class Process;
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class BaseFullCPU : public BaseCPU
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{
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//Stuff that's pretty ISA independent will go here.
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public:
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typedef BaseCPU::Params Params;
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#ifdef FULL_SYSTEM
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BaseFullCPU(Params ¶ms);
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#else
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BaseFullCPU(Params ¶ms);
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#endif // FULL_SYSTEM
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};
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template <class Impl>
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class FullBetaCPU : public BaseFullCPU
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{
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public:
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//Put typedefs from the Impl here.
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typedef typename Impl::CPUPol CPUPolicy;
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typedef typename Impl::Params Params;
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typedef typename Impl::DynInstPtr DynInstPtr;
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public:
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enum Status {
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Running,
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Idle,
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Halted,
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Blocked // ?
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};
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Status _status;
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private:
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class TickEvent : public Event
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{
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private:
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FullBetaCPU<Impl> *cpu;
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public:
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TickEvent(FullBetaCPU<Impl> *c);
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void process();
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const char *description();
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};
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TickEvent tickEvent;
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/// Schedule tick event, regardless of its current state.
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void scheduleTickEvent(int delay)
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{
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if (tickEvent.squashed())
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tickEvent.reschedule(curTick + delay);
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else if (!tickEvent.scheduled())
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tickEvent.schedule(curTick + delay);
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}
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/// Unschedule tick event, regardless of its current state.
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void unscheduleTickEvent()
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{
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if (tickEvent.scheduled())
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tickEvent.squash();
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}
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public:
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void tick();
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FullBetaCPU(Params ¶ms);
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~FullBetaCPU();
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void init();
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void fullCPURegStats();
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void activateContext(int thread_num, int delay);
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void suspendContext(int thread_num);
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void deallocateContext(int thread_num);
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void haltContext(int thread_num);
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void switchOut();
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void takeOverFrom(BaseCPU *oldCPU);
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/** Get the current instruction sequence number, and increment it. */
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InstSeqNum getAndIncrementInstSeq();
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#ifdef FULL_SYSTEM
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/** Check if this address is a valid instruction address. */
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bool validInstAddr(Addr addr) { return true; }
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/** Check if this address is a valid data address. */
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bool validDataAddr(Addr addr) { return true; }
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/** Get instruction asid. */
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int getInstAsid() { return ITB_ASN_ASN(regs.ipr[ISA::IPR_ITB_ASN]); }
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/** Get data asid. */
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int getDataAsid() { return DTB_ASN_ASN(regs.ipr[ISA::IPR_DTB_ASN]); }
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#else
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bool validInstAddr(Addr addr)
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{ return process->validInstAddr(addr); }
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bool validDataAddr(Addr addr)
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{ return process->validDataAddr(addr); }
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int getInstAsid() { return asid; }
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int getDataAsid() { return asid; }
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#endif
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//
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// New accessors for new decoder.
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//
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uint64_t readIntReg(int reg_idx);
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float readFloatRegSingle(int reg_idx);
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double readFloatRegDouble(int reg_idx);
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uint64_t readFloatRegInt(int reg_idx);
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void setIntReg(int reg_idx, uint64_t val);
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void setFloatRegSingle(int reg_idx, float val);
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void setFloatRegDouble(int reg_idx, double val);
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void setFloatRegInt(int reg_idx, uint64_t val);
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uint64_t readPC();
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void setNextPC(uint64_t val);
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void setPC(Addr new_PC);
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/** Function to add instruction onto the head of the list of the
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* instructions. Used when new instructions are fetched.
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*/
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void addInst(DynInstPtr &inst);
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/** Function to tell the CPU that an instruction has completed. */
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void instDone();
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/** Remove all instructions in back of the given instruction, but leave
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* that instruction in the list. This is useful in a squash, when there
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* are instructions in this list that don't exist in structures such as
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* the ROB. The instruction doesn't have to be the last instruction in
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* the list, but will be once this function completes.
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* @todo: Remove only up until that inst? Squashed inst is most likely
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* valid.
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*/
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void removeBackInst(DynInstPtr &inst);
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/** Remove an instruction from the front of the list. It is expected
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* that there are no instructions in front of it (that is, none are older
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* than the instruction being removed). Used when retiring instructions.
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* @todo: Remove the argument to this function, and just have it remove
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* last instruction once it's verified that commit has the same ordering
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* as the instruction list.
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*/
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void removeFrontInst(DynInstPtr &inst);
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/** Remove all instructions that are not currently in the ROB. */
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void removeInstsNotInROB();
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/** Remove all instructions younger than the given sequence number. */
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void removeInstsUntil(const InstSeqNum &seq_num);
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/** Remove all instructions from the list. */
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void removeAllInsts();
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void dumpInsts();
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/** Basically a wrapper function so that instructions executed at
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* commit can tell the instruction queue that they have completed.
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* Eventually this hack should be removed.
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*/
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void wakeDependents(DynInstPtr &inst);
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public:
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/** List of all the instructions in flight. */
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list<DynInstPtr> instList;
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//not sure these should be private.
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protected:
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/** The fetch stage. */
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typename CPUPolicy::Fetch fetch;
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/** The fetch stage's status. */
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typename CPUPolicy::Fetch::Status fetchStatus;
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/** The decode stage. */
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typename CPUPolicy::Decode decode;
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/** The decode stage's status. */
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typename CPUPolicy::Decode::Status decodeStatus;
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/** The dispatch stage. */
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typename CPUPolicy::Rename rename;
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/** The dispatch stage's status. */
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typename CPUPolicy::Rename::Status renameStatus;
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/** The issue/execute/writeback stages. */
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typename CPUPolicy::IEW iew;
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/** The issue/execute/writeback stage's status. */
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typename CPUPolicy::IEW::Status iewStatus;
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/** The commit stage. */
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typename CPUPolicy::Commit commit;
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/** The fetch stage's status. */
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typename CPUPolicy::Commit::Status commitStatus;
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//Might want to just pass these objects in to the constructors of the
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//appropriate stage. regFile is in iew, freeList in dispatch, renameMap
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//in dispatch, and the rob in commit.
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/** The register file. */
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typename CPUPolicy::RegFile regFile;
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/** The free list. */
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typename CPUPolicy::FreeList freeList;
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/** The rename map. */
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typename CPUPolicy::RenameMap renameMap;
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/** The re-order buffer. */
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typename CPUPolicy::ROB rob;
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public:
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/** Typedefs from the Impl to get the structs that each of the
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* time buffers should use.
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*/
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typedef typename CPUPolicy::TimeStruct TimeStruct;
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typedef typename CPUPolicy::FetchStruct FetchStruct;
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typedef typename CPUPolicy::DecodeStruct DecodeStruct;
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typedef typename CPUPolicy::RenameStruct RenameStruct;
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typedef typename CPUPolicy::IEWStruct IEWStruct;
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/** The main time buffer to do backwards communication. */
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TimeBuffer<TimeStruct> timeBuffer;
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/** The fetch stage's instruction queue. */
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TimeBuffer<FetchStruct> fetchQueue;
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/** The decode stage's instruction queue. */
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TimeBuffer<DecodeStruct> decodeQueue;
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/** The rename stage's instruction queue. */
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TimeBuffer<RenameStruct> renameQueue;
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/** The IEW stage's instruction queue. */
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TimeBuffer<IEWStruct> iewQueue;
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public:
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/** The temporary exec context to support older accessors. */
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ExecContext *xc;
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/** Temporary function to get pointer to exec context. */
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ExecContext *xcBase() { return xc; }
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InstSeqNum globalSeqNum;
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#ifdef FULL_SYSTEM
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System *system;
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MemoryController *memCtrl;
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PhysicalMemory *physmem;
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AlphaITB *itb;
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AlphaDTB *dtb;
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// SWContext *swCtx;
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#else
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Process *process;
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// Address space ID. Note that this is used for TIMING cache
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// simulation only; all functional memory accesses should use
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// one of the FunctionalMemory pointers above.
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short asid;
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#endif
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FunctionalMemory *mem;
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MemInterface *icacheInterface;
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MemInterface *dcacheInterface;
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bool deferRegistration;
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Counter numInsts;
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Counter funcExeInst;
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};
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#endif
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