SConscript: Include new files. arch/alpha/isa_desc: Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them. arch/alpha/isa_traits.hh: Add enum for total number of data registers. arch/isa_parser.py: base/traceflags.py: Include new light-weight OoO CPU model. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Changes to abstract more away from the base dyn inst class. cpu/beta_cpu/2bit_local_pred.cc: cpu/beta_cpu/2bit_local_pred.hh: cpu/beta_cpu/tournament_pred.cc: cpu/beta_cpu/tournament_pred.hh: Remove redundant SatCounter class. cpu/beta_cpu/alpha_dyn_inst.cc: cpu/beta_cpu/alpha_full_cpu.cc: cpu/beta_cpu/alpha_full_cpu.hh: cpu/beta_cpu/bpred_unit.cc: cpu/beta_cpu/inst_queue.cc: cpu/beta_cpu/mem_dep_unit.cc: cpu/beta_cpu/ras.cc: cpu/beta_cpu/rename_map.cc: cpu/beta_cpu/rename_map.hh: cpu/beta_cpu/rob.cc: Fix for gcc-3.4 cpu/beta_cpu/alpha_dyn_inst.hh: cpu/beta_cpu/alpha_dyn_inst_impl.hh: Fixes for gcc-3.4. Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst. cpu/beta_cpu/alpha_full_cpu_builder.cc: Make params match the current params inherited from BaseCPU. cpu/beta_cpu/alpha_full_cpu_impl.hh: Fixes for gcc-3.4 cpu/beta_cpu/full_cpu.cc: Use new params pointer in BaseCPU. Fix for gcc-3.4. cpu/beta_cpu/full_cpu.hh: Use new params class from BaseCPU. cpu/beta_cpu/iew_impl.hh: Remove unused function. cpu/simple_cpu/simple_cpu.cc: Remove unused global variable. cpu/static_inst.hh: Include OoODynInst for new lightweight OoO CPU --HG-- extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
508 lines
12 KiB
C++
508 lines
12 KiB
C++
#ifndef __SIMPLE_FULL_CPU_CC__
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#define __SIMPLE_FULL_CPU_CC__
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#ifdef FULL_SYSTEM
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#include "sim/system.hh"
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#else
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#include "sim/process.hh"
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#endif
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#include "sim/universe.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/beta_cpu/full_cpu.hh"
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#include "cpu/beta_cpu/alpha_impl.hh"
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#include "cpu/beta_cpu/alpha_dyn_inst.hh"
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using namespace std;
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BaseFullCPU::BaseFullCPU(Params ¶ms)
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: BaseCPU(¶ms)
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{
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}
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template <class Impl>
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FullBetaCPU<Impl>::TickEvent::TickEvent(FullBetaCPU<Impl> *c)
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: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
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{
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::TickEvent::process()
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{
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cpu->tick();
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}
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template <class Impl>
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const char *
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FullBetaCPU<Impl>::TickEvent::description()
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{
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return "FullBetaCPU tick event";
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}
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//Call constructor to all the pipeline stages here
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template <class Impl>
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FullBetaCPU<Impl>::FullBetaCPU(Params ¶ms)
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#ifdef FULL_SYSTEM
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: BaseFullCPU(params),
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#else
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: BaseFullCPU(params),
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#endif // FULL_SYSTEM
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tickEvent(this),
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fetch(params),
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decode(params),
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rename(params),
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iew(params),
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commit(params),
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regFile(params.numPhysIntRegs, params.numPhysFloatRegs),
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freeList(Impl::ISA::NumIntRegs, params.numPhysIntRegs,
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Impl::ISA::NumFloatRegs, params.numPhysFloatRegs),
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renameMap(Impl::ISA::NumIntRegs, params.numPhysIntRegs,
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Impl::ISA::NumFloatRegs, params.numPhysFloatRegs,
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Impl::ISA::NumMiscRegs,
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Impl::ISA::ZeroReg,
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Impl::ISA::ZeroReg + Impl::ISA::NumIntRegs),
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rob(params.numROBEntries, params.squashWidth),
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// What to pass to these time buffers?
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// For now just have these time buffers be pretty big.
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timeBuffer(5, 5),
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fetchQueue(5, 5),
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decodeQueue(5, 5),
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renameQueue(5, 5),
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iewQueue(5, 5),
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xc(NULL),
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globalSeqNum(1),
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#ifdef FULL_SYSTEM
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system(params.system),
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memCtrl(system->memCtrl),
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physmem(system->physmem),
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itb(params.itb),
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dtb(params.dtb),
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mem(params.mem),
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#else
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process(params.process),
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asid(params.asid),
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mem(process->getMemory()),
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#endif // FULL_SYSTEM
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icacheInterface(params.icacheInterface),
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dcacheInterface(params.dcacheInterface),
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deferRegistration(params.defReg),
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numInsts(0),
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funcExeInst(0)
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{
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_status = Idle;
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#ifdef FULL_SYSTEM
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xc = new ExecContext(this, 0, system, itb, dtb, mem);
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// initialize CPU, including PC
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TheISA::initCPU(&xc->regs);
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#else
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DPRINTF(FullCPU, "FullCPU: Process's starting PC is %#x, process is %#x",
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process->prog_entry, process);
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xc = new ExecContext(this, /* thread_num */ 0, process, /* asid */ 0);
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assert(process->getMemory() != NULL);
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assert(mem != NULL);
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#endif // !FULL_SYSTEM
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execContexts.push_back(xc);
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// The stages also need their CPU pointer setup. However this must be
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// done at the upper level CPU because they have pointers to the upper
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// level CPU, and not this FullBetaCPU.
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// Give each of the stages the time buffer they will use.
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fetch.setTimeBuffer(&timeBuffer);
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decode.setTimeBuffer(&timeBuffer);
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rename.setTimeBuffer(&timeBuffer);
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iew.setTimeBuffer(&timeBuffer);
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commit.setTimeBuffer(&timeBuffer);
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// Also setup each of the stages' queues.
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fetch.setFetchQueue(&fetchQueue);
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decode.setFetchQueue(&fetchQueue);
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decode.setDecodeQueue(&decodeQueue);
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rename.setDecodeQueue(&decodeQueue);
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rename.setRenameQueue(&renameQueue);
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iew.setRenameQueue(&renameQueue);
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iew.setIEWQueue(&iewQueue);
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commit.setIEWQueue(&iewQueue);
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commit.setRenameQueue(&renameQueue);
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// Setup the rename map for whichever stages need it.
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rename.setRenameMap(&renameMap);
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iew.setRenameMap(&renameMap);
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// Setup the free list for whichever stages need it.
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rename.setFreeList(&freeList);
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renameMap.setFreeList(&freeList);
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// Setup the ROB for whichever stages need it.
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commit.setROB(&rob);
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}
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template <class Impl>
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FullBetaCPU<Impl>::~FullBetaCPU()
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{
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::fullCPURegStats()
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{
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// Register any of the FullCPU's stats here.
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::tick()
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{
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DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullBetaCPU.\n");
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//Tick each of the stages if they're actually running.
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//Will want to figure out a way to unschedule itself if they're all
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//going to be idle for a long time.
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fetch.tick();
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decode.tick();
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rename.tick();
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iew.tick();
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commit.tick();
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// Now advance the time buffers, unless the stage is stalled.
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timeBuffer.advance();
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fetchQueue.advance();
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decodeQueue.advance();
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renameQueue.advance();
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iewQueue.advance();
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if (_status == Running && !tickEvent.scheduled())
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tickEvent.schedule(curTick + 1);
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::init()
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{
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if(!deferRegistration)
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{
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this->registerExecContexts();
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// Need to do a copy of the xc->regs into the CPU's regfile so
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// that it can start properly.
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// First loop through the integer registers.
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for (int i = 0; i < Impl::ISA::NumIntRegs; ++i)
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{
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regFile.intRegFile[i] = xc->regs.intRegFile[i];
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}
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// Then loop through the floating point registers.
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for (int i = 0; i < Impl::ISA::NumFloatRegs; ++i)
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{
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regFile.floatRegFile[i].d = xc->regs.floatRegFile.d[i];
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regFile.floatRegFile[i].q = xc->regs.floatRegFile.q[i];
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}
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// Then loop through the misc registers.
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regFile.miscRegs.fpcr = xc->regs.miscRegs.fpcr;
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regFile.miscRegs.uniq = xc->regs.miscRegs.uniq;
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regFile.miscRegs.lock_flag = xc->regs.miscRegs.lock_flag;
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regFile.miscRegs.lock_addr = xc->regs.miscRegs.lock_addr;
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// Then finally set the PC and the next PC.
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regFile.pc = xc->regs.pc;
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regFile.npc = xc->regs.npc;
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}
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::activateContext(int thread_num, int delay)
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{
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// Needs to set each stage to running as well.
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scheduleTickEvent(delay);
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_status = Running;
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::suspendContext(int thread_num)
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{
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panic("suspendContext unimplemented!");
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::deallocateContext(int thread_num)
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{
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panic("deallocateContext unimplemented!");
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::haltContext(int thread_num)
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{
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panic("haltContext unimplemented!");
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::switchOut()
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{
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panic("FullBetaCPU does not have a switch out function.\n");
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
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{
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BaseCPU::takeOverFrom(oldCPU);
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assert(!tickEvent.scheduled());
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// Set all status's to active, schedule the
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// CPU's tick event.
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tickEvent.schedule(curTick);
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for (int i = 0; i < execContexts.size(); ++i) {
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execContexts[i]->activate();
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}
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// Switch out the other CPU.
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oldCPU->switchOut();
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}
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template <class Impl>
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InstSeqNum
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FullBetaCPU<Impl>::getAndIncrementInstSeq()
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{
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// Hopefully this works right.
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return globalSeqNum++;
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}
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template <class Impl>
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uint64_t
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FullBetaCPU<Impl>::readIntReg(int reg_idx)
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{
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return regFile.readIntReg(reg_idx);
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}
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template <class Impl>
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float
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FullBetaCPU<Impl>::readFloatRegSingle(int reg_idx)
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{
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return regFile.readFloatRegSingle(reg_idx);
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}
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template <class Impl>
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double
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FullBetaCPU<Impl>::readFloatRegDouble(int reg_idx)
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{
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return regFile.readFloatRegDouble(reg_idx);
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}
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template <class Impl>
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uint64_t
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FullBetaCPU<Impl>::readFloatRegInt(int reg_idx)
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{
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return regFile.readFloatRegInt(reg_idx);
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::setIntReg(int reg_idx, uint64_t val)
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{
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regFile.setIntReg(reg_idx, val);
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::setFloatRegSingle(int reg_idx, float val)
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{
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regFile.setFloatRegSingle(reg_idx, val);
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::setFloatRegDouble(int reg_idx, double val)
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{
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regFile.setFloatRegDouble(reg_idx, val);
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::setFloatRegInt(int reg_idx, uint64_t val)
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{
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regFile.setFloatRegInt(reg_idx, val);
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}
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template <class Impl>
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uint64_t
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FullBetaCPU<Impl>::readPC()
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{
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return regFile.readPC();
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::setNextPC(uint64_t val)
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{
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regFile.setNextPC(val);
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::setPC(Addr new_PC)
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{
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regFile.setPC(new_PC);
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::addInst(DynInstPtr &inst)
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{
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instList.push_back(inst);
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::instDone()
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{
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// Keep an instruction count.
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numInsts++;
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// Check for instruction-count-based events.
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comInstEventQueue[0]->serviceEvents(numInsts);
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::removeBackInst(DynInstPtr &inst)
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{
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DynInstPtr inst_to_delete;
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// Walk through the instruction list, removing any instructions
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// that were inserted after the given instruction, inst.
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while (instList.back() != inst)
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{
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assert(!instList.empty());
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// Obtain the pointer to the instruction.
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inst_to_delete = instList.back();
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DPRINTF(FullCPU, "FullCPU: Removing instruction %i, PC %#x\n",
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inst_to_delete->seqNum, inst_to_delete->readPC());
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// Remove the instruction from the list.
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instList.pop_back();
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// Mark it as squashed.
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inst_to_delete->setSquashed();
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}
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::removeFrontInst(DynInstPtr &inst)
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{
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DynInstPtr inst_to_remove;
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// The front instruction should be the same one being asked to be removed.
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assert(instList.front() == inst);
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// Remove the front instruction.
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inst_to_remove = inst;
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instList.pop_front();
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DPRINTF(FullCPU, "FullCPU: Removing committed instruction %#x, PC %#x\n",
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inst_to_remove, inst_to_remove->readPC());
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::removeInstsNotInROB()
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{
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DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction "
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"list.\n");
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DynInstPtr rob_tail = rob.readTailInst();
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removeBackInst(rob_tail);
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num)
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{
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DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction "
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"list.\n");
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DynInstPtr inst_to_delete;
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while (instList.back()->seqNum > seq_num) {
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assert(!instList.empty());
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// Obtain the pointer to the instruction.
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inst_to_delete = instList.back();
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DPRINTF(FullCPU, "FullCPU: Removing instruction %i, PC %#x\n",
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inst_to_delete->seqNum, inst_to_delete->readPC());
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// Remove the instruction from the list.
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instList.pop_back();
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// Mark it as squashed.
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inst_to_delete->setSquashed();
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}
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::removeAllInsts()
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{
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instList.clear();
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::dumpInsts()
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{
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int num = 0;
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typename list<DynInstPtr>::iterator inst_list_it = instList.begin();
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while (inst_list_it != instList.end())
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{
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cprintf("Instruction:%i\nPC:%#x\nSN:%lli\nIssued:%i\nSquashed:%i\n\n",
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num, (*inst_list_it)->readPC(), (*inst_list_it)->seqNum,
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(*inst_list_it)->isIssued(), (*inst_list_it)->isSquashed());
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inst_list_it++;
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++num;
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}
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}
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template <class Impl>
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void
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FullBetaCPU<Impl>::wakeDependents(DynInstPtr &inst)
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{
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iew.wakeDependents(inst);
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}
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// Forward declaration of FullBetaCPU.
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template class FullBetaCPU<AlphaSimpleImpl>;
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#endif // __SIMPLE_FULL_CPU_HH__
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