gem5/cpu/beta_cpu/free_list.hh
Kevin Lim 2fb632dbda Check in of various updates to the CPU. Mainly adds in stats, improves
branch prediction, and makes memory dependence work properly.

SConscript:
    Added return address stack, tournament predictor.
cpu/base_cpu.cc:
    Added debug break and print statements.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
    Comment out possibly unneeded variables.
cpu/beta_cpu/2bit_local_pred.cc:
    2bit predictor no longer speculatively updates itself.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Comment formatting.
cpu/beta_cpu/alpha_full_cpu.hh:
    Formatting
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Added new parameters for branch predictors, and IQ parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Register stats.
cpu/beta_cpu/alpha_params.hh:
    Added parameters for IQ, branch predictors, and store sets.
cpu/beta_cpu/bpred_unit.cc:
    Removed one class.
cpu/beta_cpu/bpred_unit.hh:
    Add in RAS, stats.  Changed branch predictor unit functionality
    so that it holds a history of past branches so it can update, and also
    hold a proper history of the RAS so it can be restored on branch
    mispredicts.
cpu/beta_cpu/bpred_unit_impl.hh:
    Added in stats, history of branches, RAS.  Now bpred unit actually
    modifies the instruction's predicted next PC.
cpu/beta_cpu/btb.cc:
    Add in sanity checks.
cpu/beta_cpu/comm.hh:
    Add in communication where needed, remove it where it's not.
cpu/beta_cpu/commit.hh:
cpu/beta_cpu/rename.hh:
cpu/beta_cpu/rename_impl.hh:
    Add in stats.
cpu/beta_cpu/commit_impl.hh:
    Stats, update what is sent back on branch mispredict.
cpu/beta_cpu/cpu_policy.hh:
    Change the bpred unit being used.
cpu/beta_cpu/decode.hh:
cpu/beta_cpu/decode_impl.hh:
    Stats.
cpu/beta_cpu/fetch.hh:
    Stats, change squash so it can handle squashes from decode differently
    than squashes from commit.
cpu/beta_cpu/fetch_impl.hh:
    Add in stats.  Change how a cache line is fetched.  Update to work with
    caches.  Also have separate functions for different behavior if squash
    is coming from decode vs commit.
cpu/beta_cpu/free_list.hh:
    Remove some old comments.
cpu/beta_cpu/full_cpu.cc:
cpu/beta_cpu/full_cpu.hh:
    Added function to remove instructions from back of instruction list
    until a certain sequence number.
cpu/beta_cpu/iew.hh:
    Stats, separate squashing behavior due to branches vs memory.
cpu/beta_cpu/iew_impl.hh:
    Stats, separate squashing behavior for branches vs memory.
cpu/beta_cpu/inst_queue.cc:
    Debug stuff
cpu/beta_cpu/inst_queue.hh:
    Stats, change how mem dep unit works, debug stuff
cpu/beta_cpu/inst_queue_impl.hh:
    Stats, change how mem dep unit works, debug stuff.  Also add in
    parameters that used to be hardcoded.
cpu/beta_cpu/mem_dep_unit.hh:
cpu/beta_cpu/mem_dep_unit_impl.hh:
    Add in stats, change how memory dependence unit works.  It now holds
    the memory instructions that are waiting for their memory dependences
    to resolve.  It provides which instructions are ready directly to the
    IQ.
cpu/beta_cpu/regfile.hh:
    Fix up sanity checks.
cpu/beta_cpu/rename_map.cc:
    Fix loop variable type.
cpu/beta_cpu/rob_impl.hh:
    Remove intermediate DynInstPtr
cpu/beta_cpu/store_set.cc:
    Add in debugging statements.
cpu/beta_cpu/store_set.hh:
    Reorder function arguments to match the rest of the calls.

--HG--
extra : convert_revision : aabf9b1fecd1d743265dfc3b174d6159937c6f44
2004-10-21 18:02:36 -04:00

169 lines
4.4 KiB
C++

#ifndef __FREE_LIST_HH__
#define __FREE_LIST_HH__
#include <iostream>
#include <queue>
#include "arch/alpha/isa_traits.hh"
#include "cpu/beta_cpu/comm.hh"
#include "base/traceflags.hh"
#include "base/trace.hh"
/**
* FreeList class that simply holds the list of free integer and floating
* point registers. Can request for a free register of either type, and
* also send back free registers of either type. This is a very simple
* class, but it should be sufficient for most implementations. Like all
* other classes, it assumes that the indices for the floating point
* registers starts after the integer registers end. Hence the variable
* numPhysicalIntRegs is logically equivalent to the baseFP dependency.
* Note that
* while this most likely should be called FreeList, the name "FreeList"
* is used in a typedef within the CPU Policy, and therefore no class
* can be named simply "FreeList".
* @todo: Give a better name to the base FP dependency.
*/
class SimpleFreeList
{
public:
private:
/** The list of free integer registers. */
std::queue<PhysRegIndex> freeIntRegs;
/** The list of free floating point registers. */
std::queue<PhysRegIndex> freeFloatRegs;
/** Number of logical integer registers. */
int numLogicalIntRegs;
/** Number of physical integer registers. */
int numPhysicalIntRegs;
/** Number of logical floating point registers. */
int numLogicalFloatRegs;
/** Number of physical floating point registers. */
int numPhysicalFloatRegs;
/** Total number of physical registers. */
int numPhysicalRegs;
/** DEBUG stuff below. */
std::vector<int> freeIntRegsScoreboard;
std::vector<bool> freeFloatRegsScoreboard;
public:
SimpleFreeList(unsigned _numLogicalIntRegs,
unsigned _numPhysicalIntRegs,
unsigned _numLogicalFloatRegs,
unsigned _numPhysicalFloatRegs);
PhysRegIndex getIntReg();
PhysRegIndex getFloatReg();
void addReg(PhysRegIndex freed_reg);
void addIntReg(PhysRegIndex freed_reg);
void addFloatReg(PhysRegIndex freed_reg);
bool hasFreeIntRegs()
{ return !freeIntRegs.empty(); }
bool hasFreeFloatRegs()
{ return !freeFloatRegs.empty(); }
int numFreeIntRegs()
{ return freeIntRegs.size(); }
int numFreeFloatRegs()
{ return freeFloatRegs.size(); }
};
inline PhysRegIndex
SimpleFreeList::getIntReg()
{
DPRINTF(Rename, "FreeList: Trying to get free integer register.\n");
if (freeIntRegs.empty()) {
panic("No free integer registers!");
}
PhysRegIndex free_reg = freeIntRegs.front();
freeIntRegs.pop();
// DEBUG
assert(freeIntRegsScoreboard[free_reg]);
freeIntRegsScoreboard[free_reg] = 0;
return(free_reg);
}
inline PhysRegIndex
SimpleFreeList::getFloatReg()
{
DPRINTF(Rename, "FreeList: Trying to get free float register.\n");
if (freeFloatRegs.empty()) {
panic("No free integer registers!");
}
PhysRegIndex free_reg = freeFloatRegs.front();
freeFloatRegs.pop();
// DEBUG
assert(freeFloatRegsScoreboard[free_reg]);
freeFloatRegsScoreboard[free_reg] = 0;
return(free_reg);
}
inline void
SimpleFreeList::addReg(PhysRegIndex freed_reg)
{
DPRINTF(Rename, "Freelist: Freeing register %i.\n", freed_reg);
//Might want to add in a check for whether or not this register is
//already in there. A bit vector or something similar would be useful.
if (freed_reg < numPhysicalIntRegs) {
freeIntRegs.push(freed_reg);
// DEBUG
assert(freeIntRegsScoreboard[freed_reg] == false);
freeIntRegsScoreboard[freed_reg] = 1;
} else if (freed_reg < numPhysicalRegs) {
freeFloatRegs.push(freed_reg);
// DEBUG
assert(freeFloatRegsScoreboard[freed_reg] == false);
freeFloatRegsScoreboard[freed_reg] = 1;
}
}
inline void
SimpleFreeList::addIntReg(PhysRegIndex freed_reg)
{
DPRINTF(Rename, "Freelist: Freeing int register %i.\n", freed_reg);
// DEBUG
assert(!freeIntRegsScoreboard[freed_reg]);
freeIntRegsScoreboard[freed_reg] = 1;
freeIntRegs.push(freed_reg);
}
inline void
SimpleFreeList::addFloatReg(PhysRegIndex freed_reg)
{
DPRINTF(Rename, "Freelist: Freeing float register %i.\n", freed_reg);
// DEBUG
assert(!freeFloatRegsScoreboard[freed_reg]);
freeFloatRegsScoreboard[freed_reg] = 1;
freeFloatRegs.push(freed_reg);
}
#endif // __FREE_LIST_HH__