SConscript: Remove efence option from automatically being used. --HG-- extra : convert_revision : 466bb8077aa341db0b409720e2a73535b1fa6b69
391 lines
12 KiB
C++
391 lines
12 KiB
C++
#include "cpu/beta_cpu/decode.hh"
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template<class Impl>
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SimpleDecode<Impl>::SimpleDecode(Params ¶ms)
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: renameToDecodeDelay(params.renameToDecodeDelay),
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iewToDecodeDelay(params.iewToDecodeDelay),
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commitToDecodeDelay(params.commitToDecodeDelay),
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fetchToDecodeDelay(params.fetchToDecodeDelay),
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decodeWidth(params.decodeWidth),
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numInst(0)
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{
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DPRINTF(Decode, "Decode: decodeWidth=%i.\n", decodeWidth);
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_status = Idle;
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}
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template <class Impl>
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void
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SimpleDecode<Impl>::regStats()
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{
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decodeIdleCycles
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.name(name() + ".decodeIdleCycles")
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.desc("Number of cycles decode is idle")
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.prereq(decodeIdleCycles);
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decodeBlockedCycles
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.name(name() + ".decodeBlockedCycles")
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.desc("Number of cycles decode is blocked")
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.prereq(decodeBlockedCycles);
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decodeUnblockCycles
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.name(name() + ".decodeUnblockCycles")
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.desc("Number of cycles decode is unblocking")
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.prereq(decodeUnblockCycles);
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decodeSquashCycles
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.name(name() + ".decodeSquashCycles")
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.desc("Number of cycles decode is squashing")
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.prereq(decodeSquashCycles);
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decodeBranchMispred
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.name(name() + ".decodeBranchMispred")
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.desc("Number of times decode detected a branch misprediction")
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.prereq(decodeBranchMispred);
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decodeControlMispred
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.name(name() + ".decodeControlMispred")
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.desc("Number of times decode detected an instruction incorrectly"
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" predicted as a control")
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.prereq(decodeControlMispred);
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decodeDecodedInsts
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.name(name() + ".decodeDecodedInsts")
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.desc("Number of instructions handled by decode")
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.prereq(decodeDecodedInsts);
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decodeSquashedInsts
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.name(name() + ".decodeSquashedInsts")
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.desc("Number of squashed instructions handled by decode")
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.prereq(decodeSquashedInsts);
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}
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template<class Impl>
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void
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SimpleDecode<Impl>::setCPU(FullCPU *cpu_ptr)
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{
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DPRINTF(Decode, "Decode: Setting CPU pointer.\n");
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cpu = cpu_ptr;
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}
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template<class Impl>
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void
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SimpleDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
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{
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DPRINTF(Decode, "Decode: Setting time buffer pointer.\n");
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timeBuffer = tb_ptr;
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// Setup wire to write information back to fetch.
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toFetch = timeBuffer->getWire(0);
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// Create wires to get information from proper places in time buffer.
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fromRename = timeBuffer->getWire(-renameToDecodeDelay);
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fromIEW = timeBuffer->getWire(-iewToDecodeDelay);
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fromCommit = timeBuffer->getWire(-commitToDecodeDelay);
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}
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template<class Impl>
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void
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SimpleDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
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{
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DPRINTF(Decode, "Decode: Setting decode queue pointer.\n");
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decodeQueue = dq_ptr;
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// Setup wire to write information to proper place in decode queue.
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toRename = decodeQueue->getWire(0);
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}
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template<class Impl>
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void
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SimpleDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
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{
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DPRINTF(Decode, "Decode: Setting fetch queue pointer.\n");
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fetchQueue = fq_ptr;
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// Setup wire to read information from fetch queue.
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fromFetch = fetchQueue->getWire(-fetchToDecodeDelay);
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}
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template<class Impl>
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void
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SimpleDecode<Impl>::block()
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{
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DPRINTF(Decode, "Decode: Blocking.\n");
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// Set the status to Blocked.
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_status = Blocked;
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// Add the current inputs to the skid buffer so they can be
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// reprocessed when this stage unblocks.
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skidBuffer.push(*fromFetch);
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// Note that this stage only signals previous stages to stall when
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// it is the cause of the stall originates at this stage. Otherwise
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// the previous stages are expected to check all possible stall signals.
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}
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template<class Impl>
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inline void
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SimpleDecode<Impl>::unblock()
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{
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DPRINTF(Decode, "Decode: Unblocking, going to remove "
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"instructions from skid buffer.\n");
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// Remove the now processed instructions from the skid buffer.
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skidBuffer.pop();
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// If there's still information in the skid buffer, then
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// continue to tell previous stages to stall. They will be
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// able to restart once the skid buffer is empty.
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if (!skidBuffer.empty()) {
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toFetch->decodeInfo.stall = true;
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} else {
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DPRINTF(Decode, "Decode: Finished unblocking.\n");
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_status = Running;
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}
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}
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// This squash is specifically for when Decode detects a PC-relative branch
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// was predicted incorrectly.
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template<class Impl>
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void
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SimpleDecode<Impl>::squash(DynInstPtr &inst)
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{
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DPRINTF(Decode, "Decode: Squashing due to incorrect branch prediction "
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"detected at decode.\n");
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Addr new_PC = inst->readNextPC();
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toFetch->decodeInfo.branchMispredict = true;
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toFetch->decodeInfo.doneSeqNum = inst->seqNum;
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toFetch->decodeInfo.predIncorrect = true;
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toFetch->decodeInfo.squash = true;
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toFetch->decodeInfo.nextPC = new_PC;
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toFetch->decodeInfo.branchTaken = true;
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// Set status to squashing.
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_status = Squashing;
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// Maybe advance the time buffer? Not sure what to do in the normal
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// case.
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// Clear the skid buffer in case it has any data in it.
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while (!skidBuffer.empty())
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{
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skidBuffer.pop();
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}
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}
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template<class Impl>
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void
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SimpleDecode<Impl>::squash()
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{
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DPRINTF(Decode, "Decode: Squashing.\n");
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// Set status to squashing.
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_status = Squashing;
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// Maybe advance the time buffer? Not sure what to do in the normal
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// case.
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// Clear the skid buffer in case it has any data in it.
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while (!skidBuffer.empty())
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{
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skidBuffer.pop();
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}
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}
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template<class Impl>
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void
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SimpleDecode<Impl>::tick()
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{
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// Decode should try to execute as many instructions as its bandwidth
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// will allow, as long as it is not currently blocked.
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if (_status != Blocked && _status != Squashing) {
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DPRINTF(Decode, "Decode: Not blocked, so attempting to run "
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"stage.\n");
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// Make sure that the skid buffer has something in it if the
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// status is unblocking.
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assert(_status == Unblocking ? !skidBuffer.empty() : 1);
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decode();
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// If the status was unblocking, then instructions from the skid
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// buffer were used. Remove those instructions and handle
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// the rest of unblocking.
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if (_status == Unblocking) {
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++decodeUnblockCycles;
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if (fromFetch->size > 0) {
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// Add the current inputs to the skid buffer so they can be
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// reprocessed when this stage unblocks.
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skidBuffer.push(*fromFetch);
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}
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unblock();
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}
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} else if (_status == Blocked) {
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++decodeBlockedCycles;
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if (fromFetch->size > 0) {
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block();
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}
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if (!fromRename->renameInfo.stall &&
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!fromIEW->iewInfo.stall &&
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!fromCommit->commitInfo.stall) {
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DPRINTF(Decode, "Decode: Stall signals cleared, going to "
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"unblock.\n");
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_status = Unblocking;
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// Continue to tell previous stage to block until this
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// stage is done unblocking.
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toFetch->decodeInfo.stall = true;
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} else {
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DPRINTF(Decode, "Decode: Still blocked.\n");
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toFetch->decodeInfo.stall = true;
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}
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if (fromCommit->commitInfo.squash ||
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fromCommit->commitInfo.robSquashing) {
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squash();
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}
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} else if (_status == Squashing) {
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++decodeSquashCycles;
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if (!fromCommit->commitInfo.squash &&
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!fromCommit->commitInfo.robSquashing) {
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_status = Running;
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} else if (fromCommit->commitInfo.squash) {
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squash();
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}
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}
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}
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template<class Impl>
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void
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SimpleDecode<Impl>::decode()
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{
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// Check time buffer if being told to squash.
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if (fromCommit->commitInfo.squash) {
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squash();
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return;
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}
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// Check time buffer if being told to stall.
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if (fromRename->renameInfo.stall ||
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fromIEW->iewInfo.stall ||
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fromCommit->commitInfo.stall)
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{
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block();
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return;
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}
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// Check fetch queue to see if instructions are available.
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// If no available instructions, do nothing, unless this stage is
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// currently unblocking.
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if (fromFetch->size == 0 && _status != Unblocking) {
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DPRINTF(Decode, "Decode: Nothing to do, breaking out early.\n");
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// Should I change the status to idle?
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++decodeIdleCycles;
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return;
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}
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// Might be better to use a base DynInst * instead?
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DynInstPtr inst;
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unsigned to_rename_index = 0;
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int insts_available = _status == Unblocking ?
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skidBuffer.front().size :
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fromFetch->size;
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// Debug block...
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#if 0
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if (insts_available) {
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DPRINTF(Decode, "Decode: Instructions available.\n");
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} else {
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if (_status == Unblocking && skidBuffer.empty()) {
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DPRINTF(Decode, "Decode: No instructions available, skid buffer "
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"empty.\n");
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} else if (_status != Unblocking &&
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!fromFetch->insts[0]) {
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DPRINTF(Decode, "Decode: No instructions available, fetch queue "
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"empty.\n");
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} else {
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panic("Decode: No instructions available, unexpected condition!"
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"\n");
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}
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}
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#endif
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while (insts_available > 0)
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{
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DPRINTF(Decode, "Decode: Sending instruction to rename.\n");
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inst = _status == Unblocking ? skidBuffer.front().insts[numInst] :
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fromFetch->insts[numInst];
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DPRINTF(Decode, "Decode: Processing instruction %i with PC %#x\n",
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inst->seqNum, inst->readPC());
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if (inst->isSquashed()) {
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DPRINTF(Decode, "Decode: Instruction %i with PC %#x is "
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"squashed, skipping.\n",
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inst->seqNum, inst->readPC());
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++decodeSquashedInsts;
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++numInst;
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--insts_available;
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continue;
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}
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// This current instruction is valid, so add it into the decode
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// queue. The next instruction may not be valid, so check to
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// see if branches were predicted correctly.
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toRename->insts[to_rename_index] = inst;
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++(toRename->size);
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// Ensure that if it was predicted as a branch, it really is a
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// branch.
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if (inst->predTaken() && !inst->isControl()) {
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panic("Instruction predicted as a branch!");
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++decodeControlMispred;
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// Might want to set some sort of boolean and just do
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// a check at the end
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squash(inst);
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break;
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}
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// Go ahead and compute any PC-relative branches.
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if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
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inst->setNextPC(inst->branchTarget());
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if (inst->mispredicted()) {
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++decodeBranchMispred;
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// Might want to set some sort of boolean and just do
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// a check at the end
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squash(inst);
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break;
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}
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}
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// Normally can check if a direct branch has the right target
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// addr (either the immediate, or the branch PC + 4) and redirect
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// fetch if it's incorrect.
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// Also check if instructions have no source registers. Mark
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// them as ready to issue at any time. Not sure if this check
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// should exist here or at a later stage; however it doesn't matter
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// too much for function correctness.
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// Isn't this handled by the inst queue?
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if (inst->numSrcRegs() == 0) {
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inst->setCanIssue();
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}
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// Increment which instruction we're looking at.
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++numInst;
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++to_rename_index;
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++decodeDecodedInsts;
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--insts_available;
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}
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numInst = 0;
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}
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