c4d0ebd25c
SConscript:
Remove efence option from automatically being used.
--HG--
extra : convert_revision : 466bb8077aa341db0b409720e2a73535b1fa6b69
145 lines
4 KiB
C++
145 lines
4 KiB
C++
// Todo:
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// Add a couple of the branch fields to DynInst. Figure out where DynInst
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// should try to compute the target of a PC-relative branch. Try to avoid
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// having so many returns within the code.
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// Fix up squashing too, as it's too
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// dependent upon the iew stage continually telling it to squash.
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#ifndef __CPU_BETA_CPU_SIMPLE_DECODE_HH__
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#define __CPU_BETA_CPU_SIMPLE_DECODE_HH__
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#include <queue>
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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template<class Impl>
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class SimpleDecode
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{
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private:
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// Typedefs from the Impl.
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typedef typename Impl::ISA ISA;
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typedef typename Impl::FullCPU FullCPU;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::Params Params;
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typedef typename Impl::CPUPol CPUPol;
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// Typedefs from the CPU policy.
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typedef typename CPUPol::FetchStruct FetchStruct;
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typedef typename CPUPol::DecodeStruct DecodeStruct;
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typedef typename CPUPol::TimeStruct TimeStruct;
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// Typedefs from the ISA.
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typedef typename ISA::Addr Addr;
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public:
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// The only time decode will become blocked is if dispatch becomes
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// blocked, which means IQ or ROB is probably full.
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enum Status {
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Running,
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Idle,
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Squashing,
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Blocked,
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Unblocking
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};
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private:
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// May eventually need statuses on a per thread basis.
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Status _status;
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public:
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SimpleDecode(Params ¶ms);
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void regStats();
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void setCPU(FullCPU *cpu_ptr);
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void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
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void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
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void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
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void tick();
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void decode();
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// Might want to make squash a friend function.
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void squash();
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private:
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void block();
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inline void unblock();
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void squash(DynInstPtr &inst);
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// Interfaces to objects outside of decode.
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/** CPU interface. */
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FullCPU *cpu;
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/** Time buffer interface. */
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TimeBuffer<TimeStruct> *timeBuffer;
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/** Wire to get rename's output from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromRename;
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/** Wire to get iew's information from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromIEW;
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/** Wire to get commit's information from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromCommit;
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/** Wire to write information heading to previous stages. */
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// Might not be the best name as not only fetch will read it.
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typename TimeBuffer<TimeStruct>::wire toFetch;
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/** Decode instruction queue. */
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TimeBuffer<DecodeStruct> *decodeQueue;
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/** Wire used to write any information heading to rename. */
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typename TimeBuffer<DecodeStruct>::wire toRename;
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/** Fetch instruction queue interface. */
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TimeBuffer<FetchStruct> *fetchQueue;
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/** Wire to get fetch's output from fetch queue. */
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typename TimeBuffer<FetchStruct>::wire fromFetch;
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/** Skid buffer between fetch and decode. */
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std::queue<FetchStruct> skidBuffer;
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private:
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//Consider making these unsigned to avoid any confusion.
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/** Rename to decode delay, in ticks. */
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unsigned renameToDecodeDelay;
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/** IEW to decode delay, in ticks. */
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unsigned iewToDecodeDelay;
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/** Commit to decode delay, in ticks. */
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unsigned commitToDecodeDelay;
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/** Fetch to decode delay, in ticks. */
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unsigned fetchToDecodeDelay;
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/** The width of decode, in instructions. */
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unsigned decodeWidth;
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/** The instruction that decode is currently on. It needs to have
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* persistent state so that when a stall occurs in the middle of a
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* group of instructions, it can restart at the proper instruction.
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*/
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unsigned numInst;
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Stats::Scalar<> decodeIdleCycles;
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Stats::Scalar<> decodeBlockedCycles;
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Stats::Scalar<> decodeUnblockCycles;
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Stats::Scalar<> decodeSquashCycles;
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Stats::Scalar<> decodeBranchMispred;
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Stats::Scalar<> decodeControlMispred;
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Stats::Scalar<> decodeDecodedInsts;
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Stats::Scalar<> decodeSquashedInsts;
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};
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#endif // __CPU_BETA_CPU_SIMPLE_DECODE_HH__
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