SConscript: Remove efence option from automatically being used. --HG-- extra : convert_revision : 466bb8077aa341db0b409720e2a73535b1fa6b69
143 lines
3.2 KiB
C++
143 lines
3.2 KiB
C++
#ifndef __CPU_BETA_CPU_COMM_HH__
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#define __CPU_BETA_CPU_COMM_HH__
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#include <stdint.h>
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#include <vector>
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#include "arch/alpha/isa_traits.hh"
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#include "cpu/inst_seq.hh"
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// Find better place to put this typedef.
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// The impl might be the best place for this.
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typedef short int PhysRegIndex;
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template<class Impl>
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struct SimpleFetchSimpleDecode {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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};
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template<class Impl>
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struct SimpleDecodeSimpleRename {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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};
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template<class Impl>
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struct SimpleRenameSimpleIEW {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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};
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template<class Impl>
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struct SimpleIEWSimpleCommit {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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bool squash;
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bool branchMispredict;
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bool branchTaken;
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uint64_t mispredPC;
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uint64_t nextPC;
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unsigned globalHist;
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InstSeqNum squashedSeqNum;
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};
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template<class Impl>
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struct IssueStruct {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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};
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struct TimeBufStruct {
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struct decodeComm {
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bool squash;
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bool stall;
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bool predIncorrect;
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uint64_t branchAddr;
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InstSeqNum doneSeqNum;
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// Might want to package this kind of branch stuff into a single
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// struct as it is used pretty frequently.
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bool branchMispredict;
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bool branchTaken;
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uint64_t mispredPC;
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uint64_t nextPC;
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unsigned globalHist;
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};
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decodeComm decodeInfo;
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// Rename can't actually tell anything to squash or send a new PC back
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// because it doesn't do anything along those lines. But maybe leave
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// these fields in here to keep the stages mostly orthagonal.
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struct renameComm {
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bool squash;
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bool stall;
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uint64_t nextPC;
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};
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renameComm renameInfo;
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struct iewComm {
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bool stall;
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// Also eventually include skid buffer space.
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unsigned freeIQEntries;
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};
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iewComm iewInfo;
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struct commitComm {
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bool squash;
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bool stall;
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unsigned freeROBEntries;
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bool branchMispredict;
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bool branchTaken;
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uint64_t mispredPC;
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uint64_t nextPC;
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unsigned globalHist;
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// Think of better names here.
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// Will need to be a variety of sizes...
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// Maybe make it a vector, that way only need one object.
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std::vector<PhysRegIndex> freeRegs;
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bool robSquashing;
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// Represents the instruction that has either been retired or
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// squashed. Similar to having a single bus that broadcasts the
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// retired or squashed sequence number.
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InstSeqNum doneSeqNum;
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// Extra bits of information so that the LDSTQ only updates when it
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// needs to.
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bool commitIsStore;
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bool commitIsLoad;
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// Communication specifically to the IQ to tell the IQ that it can
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// schedule a non-speculative instruction.
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InstSeqNum nonSpecSeqNum;
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};
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commitComm commitInfo;
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};
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#endif //__CPU_BETA_CPU_COMM_HH__
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