SConscript: Include new files. arch/alpha/isa_desc: Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them. arch/alpha/isa_traits.hh: Add enum for total number of data registers. arch/isa_parser.py: base/traceflags.py: Include new light-weight OoO CPU model. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Changes to abstract more away from the base dyn inst class. cpu/beta_cpu/2bit_local_pred.cc: cpu/beta_cpu/2bit_local_pred.hh: cpu/beta_cpu/tournament_pred.cc: cpu/beta_cpu/tournament_pred.hh: Remove redundant SatCounter class. cpu/beta_cpu/alpha_dyn_inst.cc: cpu/beta_cpu/alpha_full_cpu.cc: cpu/beta_cpu/alpha_full_cpu.hh: cpu/beta_cpu/bpred_unit.cc: cpu/beta_cpu/inst_queue.cc: cpu/beta_cpu/mem_dep_unit.cc: cpu/beta_cpu/ras.cc: cpu/beta_cpu/rename_map.cc: cpu/beta_cpu/rename_map.hh: cpu/beta_cpu/rob.cc: Fix for gcc-3.4 cpu/beta_cpu/alpha_dyn_inst.hh: cpu/beta_cpu/alpha_dyn_inst_impl.hh: Fixes for gcc-3.4. Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst. cpu/beta_cpu/alpha_full_cpu_builder.cc: Make params match the current params inherited from BaseCPU. cpu/beta_cpu/alpha_full_cpu_impl.hh: Fixes for gcc-3.4 cpu/beta_cpu/full_cpu.cc: Use new params pointer in BaseCPU. Fix for gcc-3.4. cpu/beta_cpu/full_cpu.hh: Use new params class from BaseCPU. cpu/beta_cpu/iew_impl.hh: Remove unused function. cpu/simple_cpu/simple_cpu.cc: Remove unused global variable. cpu/static_inst.hh: Include OoODynInst for new lightweight OoO CPU --HG-- extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
135 lines
2.6 KiB
C++
135 lines
2.6 KiB
C++
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#include "cpu/beta_cpu/alpha_dyn_inst.hh"
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template <class Impl>
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AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
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InstSeqNum seq_num, FullCPU *cpu)
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: BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
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{
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// Make sure to have the renamed register entries set to the same
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// as the normal register entries. It will allow the IQ to work
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// without any modifications.
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for (int i = 0; i < this->staticInst->numDestRegs(); i++)
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{
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_destRegIdx[i] = this->staticInst->destRegIdx(i);
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}
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for (int i = 0; i < this->staticInst->numSrcRegs(); i++)
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{
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_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
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this->_readySrcRegIdx[i] = 0;
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}
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}
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template <class Impl>
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AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst)
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: BaseDynInst<Impl>(_staticInst)
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{
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// Make sure to have the renamed register entries set to the same
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// as the normal register entries. It will allow the IQ to work
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// without any modifications.
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for (int i = 0; i < _staticInst->numDestRegs(); i++)
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{
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_destRegIdx[i] = _staticInst->destRegIdx(i);
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}
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for (int i = 0; i < _staticInst->numSrcRegs(); i++)
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{
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_srcRegIdx[i] = _staticInst->srcRegIdx(i);
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}
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}
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template <class Impl>
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uint64_t
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AlphaDynInst<Impl>::readUniq()
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{
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return this->cpu->readUniq();
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}
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template <class Impl>
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void
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AlphaDynInst<Impl>::setUniq(uint64_t val)
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{
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this->cpu->setUniq(val);
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}
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template <class Impl>
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uint64_t
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AlphaDynInst<Impl>::readFpcr()
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{
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return this->cpu->readFpcr();
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}
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template <class Impl>
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void
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AlphaDynInst<Impl>::setFpcr(uint64_t val)
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{
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this->cpu->setFpcr(val);
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}
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#ifdef FULL_SYSTEM
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template <class Impl>
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uint64_t
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AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
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{
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return this->cpu->readIpr(idx, fault);
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}
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template <class Impl>
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Fault
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AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
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{
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return this->cpu->setIpr(idx, val);
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}
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template <class Impl>
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Fault
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AlphaDynInst<Impl>::hwrei()
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{
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return this->cpu->hwrei();
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}
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template <class Impl>
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int
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AlphaDynInst<Impl>::readIntrFlag()
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{
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return this->cpu->readIntrFlag();
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}
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template <class Impl>
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void
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AlphaDynInst<Impl>::setIntrFlag(int val)
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{
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this->cpu->setIntrFlag(val);
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}
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template <class Impl>
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bool
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AlphaDynInst<Impl>::inPalMode()
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{
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return this->cpu->inPalMode();
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}
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template <class Impl>
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void
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AlphaDynInst<Impl>::trap(Fault fault)
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{
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this->cpu->trap(fault);
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}
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template <class Impl>
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bool
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AlphaDynInst<Impl>::simPalCheck(int palFunc)
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{
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return this->cpu->simPalCheck(palFunc);
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}
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#else
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template <class Impl>
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void
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AlphaDynInst<Impl>::syscall()
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{
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this->cpu->syscall();
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}
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#endif
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