all macros in ev5.hh to inline functions or constant typed variables and make them follow our style while we're at it. All of the stuff in this file actually belongs in the ISA traits code, but this is a first step at getting things done in the right manner. arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/ev5.cc: arch/alpha/isa_desc: dev/ns_gige.cc: kern/tru64/tru64_events.cc: deal with changes in ev5.hh arch/alpha/ev5.hh: Macros are nasty, so let's get rid of them. Convert all all macros to inline functions or constant typed variables. Make them follow our style while we're at it. All of the stuff in this file actually belongs in the ISA traits code, but this is a first step at getting things done in the right manner. arch/alpha/isa_traits.hh: move some of the ev5 specific code into the isa arch/alpha/vtophys.cc: base/remote_gdb.cc: deal with isa addition cpu/exec_context.hh: be less isa specific and use the isa traits to figure out what we can. dev/alpha_console.cc: dev/pciconfigall.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart.cc: deal with changes in ev5.hh I don't believe this masking is actually necessary. We should look at removing it later. dev/ide_ctrl.cc: sort #includes deal with changes in ev5.hh --HG-- extra : convert_revision : c8a3adf0a4b1d198aefe38fc38b295abf289b08a
264 lines
7.4 KiB
C++
264 lines
7.4 KiB
C++
/*
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* Copyright (c) 2002-2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <string>
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#include "arch/alpha/vtophys.hh"
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "mem/functional_mem/physical_memory.hh"
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using namespace std;
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AlphaISA::PageTableEntry
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kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, AlphaISA::VAddr vaddr)
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{
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Addr level1_pte = ptbr + vaddr.level1();
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AlphaISA::PageTableEntry level1 = pmem->phys_read_qword(level1_pte);
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if (!level1.valid()) {
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DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr);
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return 0;
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}
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Addr level2_pte = level1.paddr() + vaddr.level2();
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AlphaISA::PageTableEntry level2 = pmem->phys_read_qword(level2_pte);
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if (!level2.valid()) {
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DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr);
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return 0;
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}
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Addr level3_pte = level2.paddr() + vaddr.level3();
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AlphaISA::PageTableEntry level3 = pmem->phys_read_qword(level3_pte);
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if (!level3.valid()) {
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DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr);
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return 0;
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}
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return level3;
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}
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Addr
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vtophys(PhysicalMemory *xc, Addr vaddr)
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{
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Addr paddr = 0;
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if (AlphaISA::IsUSeg(vaddr))
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DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
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else if (AlphaISA::IsK0Seg(vaddr))
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paddr = AlphaISA::K0Seg2Phys(vaddr);
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else
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panic("vtophys: ptbr is not set on virtual lookup");
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DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
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return paddr;
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}
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Addr
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vtophys(ExecContext *xc, Addr addr)
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{
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AlphaISA::VAddr vaddr = addr;
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Addr ptbr = xc->regs.ipr[AlphaISA::IPR_PALtemp20];
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Addr paddr = 0;
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//@todo Andrew couldn't remember why he commented some of this code
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//so I put it back in. Perhaps something to do with gdb debugging?
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if (AlphaISA::PcPAL(vaddr) && (vaddr < EV5::PalMax)) {
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paddr = vaddr & ~ULL(1);
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} else {
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if (AlphaISA::IsK0Seg(vaddr)) {
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paddr = AlphaISA::K0Seg2Phys(vaddr);
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} else if (!ptbr) {
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paddr = vaddr;
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} else {
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AlphaISA::PageTableEntry pte =
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kernel_pte_lookup(xc->physmem, ptbr, vaddr);
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if (pte.valid())
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paddr = pte.paddr() | vaddr.offset();
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}
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}
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DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
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return paddr;
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}
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uint8_t *
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ptomem(ExecContext *xc, Addr paddr, size_t len)
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{
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return xc->physmem->dma_addr(paddr, len);
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}
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uint8_t *
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vtomem(ExecContext *xc, Addr vaddr, size_t len)
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{
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Addr paddr = vtophys(xc, vaddr);
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return xc->physmem->dma_addr(paddr, len);
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}
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void
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CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen)
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{
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Addr paddr;
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char *dmaaddr;
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char *dst = (char *)dest;
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int len;
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paddr = vtophys(xc, src);
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len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
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(int)cplen);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
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assert(dmaaddr);
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memcpy(dst, dmaaddr, len);
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if (len == cplen)
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return;
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cplen -= len;
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dst += len;
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src += len;
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while (cplen > AlphaISA::PageBytes) {
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paddr = vtophys(xc, src);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
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assert(dmaaddr);
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memcpy(dst, dmaaddr, AlphaISA::PageBytes);
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cplen -= AlphaISA::PageBytes;
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dst += AlphaISA::PageBytes;
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src += AlphaISA::PageBytes;
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}
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if (cplen > 0) {
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paddr = vtophys(xc, src);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, cplen);
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assert(dmaaddr);
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memcpy(dst, dmaaddr, cplen);
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}
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}
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void
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CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen)
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{
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Addr paddr;
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char *dmaaddr;
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char *src = (char *)source;
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int len;
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paddr = vtophys(xc, dest);
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len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
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(int)cplen);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
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assert(dmaaddr);
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memcpy(dmaaddr, src, len);
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if (len == cplen)
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return;
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cplen -= len;
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src += len;
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dest += len;
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while (cplen > AlphaISA::PageBytes) {
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paddr = vtophys(xc, dest);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
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assert(dmaaddr);
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memcpy(dmaaddr, src, AlphaISA::PageBytes);
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cplen -= AlphaISA::PageBytes;
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src += AlphaISA::PageBytes;
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dest += AlphaISA::PageBytes;
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}
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if (cplen > 0) {
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paddr = vtophys(xc, dest);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, cplen);
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assert(dmaaddr);
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memcpy(dmaaddr, src, cplen);
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}
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}
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void
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CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen)
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{
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Addr paddr;
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char *dmaaddr;
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int len;
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paddr = vtophys(xc, vaddr);
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len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
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(int)maxlen);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
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assert(dmaaddr);
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char *term = (char *)memchr(dmaaddr, 0, len);
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if (term)
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len = term - dmaaddr + 1;
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memcpy(dst, dmaaddr, len);
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if (term || len == maxlen)
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return;
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maxlen -= len;
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dst += len;
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vaddr += len;
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while (maxlen > AlphaISA::PageBytes) {
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paddr = vtophys(xc, vaddr);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
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assert(dmaaddr);
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char *term = (char *)memchr(dmaaddr, 0, AlphaISA::PageBytes);
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len = term ? (term - dmaaddr + 1) : AlphaISA::PageBytes;
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memcpy(dst, dmaaddr, len);
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if (term)
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return;
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maxlen -= AlphaISA::PageBytes;
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dst += AlphaISA::PageBytes;
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vaddr += AlphaISA::PageBytes;
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}
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if (maxlen > 0) {
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paddr = vtophys(xc, vaddr);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, maxlen);
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assert(dmaaddr);
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char *term = (char *)memchr(dmaaddr, 0, maxlen);
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len = term ? (term - dmaaddr + 1) : maxlen;
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memcpy(dst, dmaaddr, len);
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maxlen -= len;
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}
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if (maxlen == 0)
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dst[maxlen] = '\0';
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}
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