541 lines
14 KiB
C++
541 lines
14 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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*/
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#include "arch/faults.hh"
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#include "arch/utility.hh"
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#include "base/cp_annotate.hh"
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#include "base/cprintf.hh"
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#include "base/inifile.hh"
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#include "base/loader/symtab.hh"
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#include "base/misc.hh"
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#include "base/pollevent.hh"
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#include "base/range.hh"
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "config/the_isa.hh"
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#include "cpu/base.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/profile.hh"
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#include "cpu/simple/base.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/smt.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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#include "mem/packet.hh"
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#include "mem/request.hh"
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#include "params/BaseSimpleCPU.hh"
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#include "sim/byteswap.hh"
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#include "sim/debug.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_object.hh"
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#include "sim/stats.hh"
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#include "sim/system.hh"
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#if FULL_SYSTEM
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#include "arch/kernel_stats.hh"
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#include "arch/stacktrace.hh"
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#include "arch/tlb.hh"
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#include "arch/vtophys.hh"
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#else // !FULL_SYSTEM
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#include "mem/mem_object.hh"
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#endif // FULL_SYSTEM
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using namespace std;
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using namespace TheISA;
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BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
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: BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
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{
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#if FULL_SYSTEM
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thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
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#else
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thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
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p->itb, p->dtb);
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#endif // !FULL_SYSTEM
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thread->setStatus(ThreadContext::Halted);
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tc = thread->getTC();
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numInst = 0;
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startNumInst = 0;
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numLoad = 0;
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startNumLoad = 0;
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lastIcacheStall = 0;
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lastDcacheStall = 0;
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threadContexts.push_back(tc);
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fetchOffset = 0;
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stayAtPC = false;
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}
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BaseSimpleCPU::~BaseSimpleCPU()
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{
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}
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void
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BaseSimpleCPU::deallocateContext(int thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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void
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BaseSimpleCPU::haltContext(int thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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void
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BaseSimpleCPU::regStats()
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{
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using namespace Stats;
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BaseCPU::regStats();
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numInsts
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.name(name() + ".num_insts")
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.desc("Number of instructions executed")
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;
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numIntAluAccesses
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.name(name() + ".num_int_alu_accesses")
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.desc("Number of integer alu accesses")
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;
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numFpAluAccesses
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.name(name() + ".num_fp_alu_accesses")
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.desc("Number of float alu accesses")
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;
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numCallsReturns
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.name(name() + ".num_func_calls")
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.desc("number of times a function call or return occured")
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;
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numCondCtrlInsts
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.name(name() + ".num_conditional_control_insts")
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.desc("number of instructions that are conditional controls")
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;
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numIntInsts
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.name(name() + ".num_int_insts")
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.desc("number of integer instructions")
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;
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numFpInsts
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.name(name() + ".num_fp_insts")
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.desc("number of float instructions")
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;
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numIntRegReads
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.name(name() + ".num_int_register_reads")
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.desc("number of times the integer registers were read")
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;
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numIntRegWrites
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.name(name() + ".num_int_register_writes")
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.desc("number of times the integer registers were written")
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;
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numFpRegReads
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.name(name() + ".num_fp_register_reads")
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.desc("number of times the floating registers were read")
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;
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numFpRegWrites
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.name(name() + ".num_fp_register_writes")
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.desc("number of times the floating registers were written")
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;
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numMemRefs
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.name(name()+".num_mem_refs")
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.desc("number of memory refs")
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;
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numStoreInsts
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.name(name() + ".num_store_insts")
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.desc("Number of store instructions")
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;
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numLoadInsts
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.name(name() + ".num_load_insts")
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.desc("Number of load instructions")
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;
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notIdleFraction
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.name(name() + ".not_idle_fraction")
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.desc("Percentage of non-idle cycles")
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;
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idleFraction
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.name(name() + ".idle_fraction")
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.desc("Percentage of idle cycles")
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;
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numBusyCycles
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.name(name() + ".num_busy_cycles")
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.desc("Number of busy cycles")
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;
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numIdleCycles
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.name(name()+".num_idle_cycles")
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.desc("Number of idle cycles")
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;
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icacheStallCycles
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.name(name() + ".icache_stall_cycles")
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.desc("ICache total stall cycles")
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.prereq(icacheStallCycles)
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;
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dcacheStallCycles
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.name(name() + ".dcache_stall_cycles")
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.desc("DCache total stall cycles")
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.prereq(dcacheStallCycles)
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;
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icacheRetryCycles
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.name(name() + ".icache_retry_cycles")
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.desc("ICache total retry cycles")
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.prereq(icacheRetryCycles)
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;
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dcacheRetryCycles
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.name(name() + ".dcache_retry_cycles")
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.desc("DCache total retry cycles")
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.prereq(dcacheRetryCycles)
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;
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idleFraction = constant(1.0) - notIdleFraction;
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numIdleCycles = idleFraction * numCycles;
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numBusyCycles = (notIdleFraction)*numCycles;
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}
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void
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BaseSimpleCPU::resetStats()
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{
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// startNumInst = numInst;
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notIdleFraction = (_status != Idle);
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}
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void
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BaseSimpleCPU::serialize(ostream &os)
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{
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SERIALIZE_ENUM(_status);
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BaseCPU::serialize(os);
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// SERIALIZE_SCALAR(inst);
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nameOut(os, csprintf("%s.xc.0", name()));
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thread->serialize(os);
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}
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void
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BaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
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{
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UNSERIALIZE_ENUM(_status);
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BaseCPU::unserialize(cp, section);
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// UNSERIALIZE_SCALAR(inst);
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thread->unserialize(cp, csprintf("%s.xc.0", section));
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}
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void
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change_thread_state(ThreadID tid, int activate, int priority)
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{
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}
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#if FULL_SYSTEM
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Addr
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BaseSimpleCPU::dbg_vtophys(Addr addr)
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{
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return vtophys(tc, addr);
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}
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#endif // FULL_SYSTEM
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#if FULL_SYSTEM
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void
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BaseSimpleCPU::wakeup()
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{
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if (thread->status() != ThreadContext::Suspended)
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return;
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DPRINTF(Quiesce,"Suspended Processor awoke\n");
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thread->activate();
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}
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#endif // FULL_SYSTEM
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void
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BaseSimpleCPU::checkForInterrupts()
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{
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#if FULL_SYSTEM
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if (checkInterrupts(tc)) {
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Fault interrupt = interrupts->getInterrupt(tc);
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if (interrupt != NoFault) {
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fetchOffset = 0;
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interrupts->updateIntrInfo(tc);
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interrupt->invoke(tc);
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predecoder.reset();
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}
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}
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#endif
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}
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void
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BaseSimpleCPU::setupFetchRequest(Request *req)
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{
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Addr instAddr = thread->instAddr();
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// set up memory request for instruction fetch
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DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
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Addr fetchPC = (instAddr & PCMask) + fetchOffset;
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req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instAddr);
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}
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void
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BaseSimpleCPU::preExecute()
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{
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// maintain $r0 semantics
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thread->setIntReg(ZeroReg, 0);
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#if THE_ISA == ALPHA_ISA
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thread->setFloatReg(ZeroReg, 0.0);
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#endif // ALPHA_ISA
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// check for instruction-count-based events
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comInstEventQueue[0]->serviceEvents(numInst);
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system->instEventQueue.serviceEvents(system->totalNumInsts);
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// decode the instruction
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inst = gtoh(inst);
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TheISA::PCState pcState = thread->pcState();
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if (isRomMicroPC(pcState.microPC())) {
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stayAtPC = false;
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curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
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curMacroStaticInst);
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} else if (!curMacroStaticInst) {
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//We're not in the middle of a macro instruction
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StaticInstPtr instPtr = NULL;
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//Predecode, ie bundle up an ExtMachInst
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//This should go away once the constructor can be set up properly
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predecoder.setTC(thread->getTC());
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//If more fetch data is needed, pass it in.
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Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
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//if(predecoder.needMoreBytes())
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predecoder.moreBytes(pcState, fetchPC, inst);
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//else
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// predecoder.process();
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//If an instruction is ready, decode it. Otherwise, we'll have to
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//fetch beyond the MachInst at the current pc.
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if (predecoder.extMachInstReady()) {
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stayAtPC = false;
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ExtMachInst machInst = predecoder.getExtMachInst(pcState);
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thread->pcState(pcState);
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instPtr = StaticInst::decode(machInst, pcState.instAddr());
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} else {
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stayAtPC = true;
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fetchOffset += sizeof(MachInst);
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}
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//If we decoded an instruction and it's microcoded, start pulling
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//out micro ops
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if (instPtr && instPtr->isMacroop()) {
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curMacroStaticInst = instPtr;
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curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
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} else {
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curStaticInst = instPtr;
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}
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} else {
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//Read the next micro op from the macro op
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curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
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}
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//If we decoded an instruction this "tick", record information about it.
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if(curStaticInst)
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{
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#if TRACING_ON
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traceData = tracer->getInstRecord(curTick(), tc,
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curStaticInst, thread->pcState(), curMacroStaticInst);
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DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
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curStaticInst->getName(), curStaticInst->machInst);
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#endif // TRACING_ON
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}
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}
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void
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BaseSimpleCPU::postExecute()
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{
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assert(curStaticInst);
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TheISA::PCState pc = tc->pcState();
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Addr instAddr = pc.instAddr();
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#if FULL_SYSTEM
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if (thread->profile) {
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bool usermode = TheISA::inUserMode(tc);
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thread->profilePC = usermode ? 1 : instAddr;
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ProfileNode *node = thread->profile->consume(tc, curStaticInst);
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if (node)
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thread->profileNode = node;
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}
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#endif
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if (curStaticInst->isMemRef()) {
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numMemRefs++;
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}
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if (curStaticInst->isLoad()) {
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++numLoad;
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comLoadEventQueue[0]->serviceEvents(numLoad);
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}
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if (CPA::available()) {
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CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr());
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}
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/* Power model statistics */
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//integer alu accesses
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if (curStaticInst->isInteger()){
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numIntAluAccesses++;
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numIntInsts++;
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}
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//float alu accesses
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if (curStaticInst->isFloating()){
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numFpAluAccesses++;
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numFpInsts++;
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}
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//number of function calls/returns to get window accesses
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if (curStaticInst->isCall() || curStaticInst->isReturn()){
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numCallsReturns++;
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}
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//the number of branch predictions that will be made
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if (curStaticInst->isCondCtrl()){
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numCondCtrlInsts++;
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}
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//result bus acceses
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if (curStaticInst->isLoad()){
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numLoadInsts++;
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}
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if (curStaticInst->isStore()){
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numStoreInsts++;
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}
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/* End power model statistics */
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traceFunctions(instAddr);
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if (traceData) {
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traceData->dump();
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delete traceData;
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traceData = NULL;
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}
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}
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void
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BaseSimpleCPU::advancePC(Fault fault)
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{
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//Since we're moving to a new pc, zero out the offset
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fetchOffset = 0;
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if (fault != NoFault) {
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curMacroStaticInst = StaticInst::nullStaticInstPtr;
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fault->invoke(tc, curStaticInst);
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predecoder.reset();
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} else {
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if (curStaticInst) {
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if (curStaticInst->isLastMicroop())
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curMacroStaticInst = StaticInst::nullStaticInstPtr;
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TheISA::PCState pcState = thread->pcState();
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TheISA::advancePC(pcState, curStaticInst);
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thread->pcState(pcState);
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}
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}
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}
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/*Fault
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BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
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{
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// translate to physical address
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Fault fault = NoFault;
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int CacheID = Op & 0x3; // Lower 3 bits identify Cache
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int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
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if(CacheID > 1)
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{
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warn("CacheOps not implemented for secondary/tertiary caches\n");
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}
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else
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{
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switch(CacheOP)
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{ // Fill Packet Type
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case 0: warn("Invalidate Cache Op\n");
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break;
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case 1: warn("Index Load Tag Cache Op\n");
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break;
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case 2: warn("Index Store Tag Cache Op\n");
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break;
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case 4: warn("Hit Invalidate Cache Op\n");
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break;
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case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
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break;
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case 6: warn("Hit Writeback\n");
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break;
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case 7: warn("Fetch & Lock Cache Op\n");
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break;
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default: warn("Unimplemented Cache Op\n");
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}
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}
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return fault;
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}*/
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