..
prefetch
sim: Call regStats of base-class as well
2016-06-06 17:16:43 +01:00
tags
mem: Split the hit_latency into tag_latency and data_latency
2016-11-30 17:10:27 -05:00
base.cc
mem: Split the hit_latency into tag_latency and data_latency
2016-11-30 17:10:27 -05:00
base.hh
mem: Make packet debug printing more uniform
2016-12-05 16:48:21 -05:00
blk.cc
mem: fix headers include order in the cache related classes
2016-05-26 11:56:24 +01:00
blk.hh
mem, cpu: Add assertions to snoop invalidation logic
2015-08-10 11:25:52 +01:00
cache.cc
mem: Ensure InvalidateReq is considered isForward by MSHRs
2016-12-05 16:48:23 -05:00
cache.hh
mem: Update mostly exclusive cache policy to cover more cases
2016-08-12 14:11:45 +01:00
Cache.py
mem: Split the hit_latency into tag_latency and data_latency
2016-11-30 17:10:27 -05:00
mshr.cc
mem: Make packet debug printing more uniform
2016-12-05 16:48:21 -05:00
mshr.hh
mem: Service only the 1st FromCPU MSHR target on ReadRespWithInv
2016-12-05 16:48:19 -05:00
mshr_queue.cc
mem: Create a separate class for the cache write buffer
2016-03-17 09:51:18 -04:00
mshr_queue.hh
mem: Adjust cache queue reserve to more conservative values
2016-03-17 09:51:22 -04:00
queue.hh
mem: change NULL to nullptr in the cache related classes
2016-05-26 11:56:24 +01:00
queue_entry.hh
mem: Create a separate class for the cache write buffer
2016-03-17 09:51:18 -04:00
SConscript
mem: Create a separate class for the cache write buffer
2016-03-17 09:51:18 -04:00
write_queue.cc
mem: Deallocate all write-queue entries when sent
2016-04-21 04:48:07 -04:00
write_queue.hh
mem: Create a separate class for the cache write buffer
2016-03-17 09:51:18 -04:00
write_queue_entry.cc
mem: change NULL to nullptr in the cache related classes
2016-05-26 11:56:24 +01:00
write_queue_entry.hh
mem: Deallocate all write-queue entries when sent
2016-04-21 04:48:07 -04:00