272 lines
9.8 KiB
C++
272 lines
9.8 KiB
C++
/*
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* Redistribution and use of this software in source and binary forms,
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* with or without modification, are permitted provided that the
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* following conditions are met:
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*
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* The software must be used only for Non-Commercial Use which means any
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* use which is NOT directed to receiving any direct monetary
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* compensation for, or commercial advantage from such use. Illustrative
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* examples of non-commercial use are academic research, personal study,
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* teaching, education and corporate research & development.
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* Illustrative examples of commercial use are distributing products for
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* commercial advantage and providing services using the software for
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* commercial advantage.
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*
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* If you wish to use this software or functionality therein that may be
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* covered by patents for commercial use, please contact:
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* Director of Intellectual Property Licensing
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* Office of Strategy and Technology
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* Hewlett-Packard Company
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* 1501 Page Mill Road
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* Palo Alto, California 94304
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*
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* Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer. Redistributions
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* in binary form must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution. Neither the name of
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* the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission. No right of
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* sublicense is granted herewith. Derivatives of the software and
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* output created using the software may be prepared, but only for
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* Non-Commercial Uses. Derivatives of the software may be shared with
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* others provided: (i) the others agree to abide by the list of
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* conditions herein which includes the Non-Commercial Use restrictions;
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* and (ii) such Derivatives of the software include the above copyright
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* notice to acknowledge the contribution from this software where
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* applicable, this list of conditions and the disclaimer below.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/x86/intregs.hh"
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#include "arch/x86/miscregs.hh"
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#include "arch/x86/segmentregs.hh"
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#include "arch/x86/utility.hh"
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#include "arch/x86/x86_traits.hh"
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namespace X86ISA {
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uint64_t getArgument(ThreadContext *tc, int number, bool fp) {
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#if FULL_SYSTEM
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panic("getArgument() not implemented for x86!\n");
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#else
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panic("getArgument() only implemented for FULL_SYSTEM\n");
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M5_DUMMY_RETURN
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#endif
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}
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# if FULL_SYSTEM
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void initCPU(ThreadContext *tc, int cpuId)
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{
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// The otherwise unmodified integer registers should be set to 0.
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for (int index = 0; index < NUM_INTREGS; index++) {
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tc->setIntReg(index, 0);
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}
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// These next two loops zero internal microcode and implicit registers.
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// They aren't specified by the ISA but are used internally by M5's
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// implementation.
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for (int index = 0; index < NumMicroIntRegs; index++) {
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tc->setIntReg(INTREG_MICRO(index), 0);
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}
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for (int index = 0; index < NumImplicitIntRegs; index++) {
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tc->setIntReg(INTREG_IMPLICIT(index), 0);
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}
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// Set integer register EAX to 0 to indicate that the optional BIST
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// passed. No BIST actually runs, but software may still check this
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// register for errors.
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tc->setIntReg(INTREG_RAX, 0);
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//The following values are dictated by the architecture for after a RESET#
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tc->setMiscReg(MISCREG_CR0, 0x0000000060000010);
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tc->setMiscReg(MISCREG_CR2, 0);
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tc->setMiscReg(MISCREG_CR3, 0);
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tc->setMiscReg(MISCREG_CR4, 0);
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tc->setMiscReg(MISCREG_CR8, 0);
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tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002);
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tc->setMiscReg(MISCREG_EFER, 0);
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SegAttr dataAttr = 0;
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dataAttr.writable = 1;
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dataAttr.readable = 1;
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dataAttr.expandDown = 0;
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dataAttr.dpl = 0;
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dataAttr.defaultSize = 0;
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for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
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tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
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tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
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tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
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tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
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}
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SegAttr codeAttr = 0;
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codeAttr.writable = 0;
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codeAttr.readable = 1;
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codeAttr.expandDown = 0;
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codeAttr.dpl = 0;
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codeAttr.defaultSize = 0;
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tc->setMiscReg(MISCREG_CS, 0xf000);
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tc->setMiscReg(MISCREG_CS_BASE, 0x00000000ffff0000);
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// This has the base value pre-added.
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tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
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tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
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tc->setPC(0x000000000000fff0 +
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tc->readMiscReg(MISCREG_CS_BASE));
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tc->setNextPC(tc->readPC() + sizeof(MachInst));
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tc->setMiscReg(MISCREG_GDTR_BASE, 0);
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tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xffff);
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tc->setMiscReg(MISCREG_IDTR_BASE, 0);
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tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
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tc->setMiscReg(MISCREG_LDTR, 0);
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tc->setMiscReg(MISCREG_LDTR_BASE, 0);
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tc->setMiscReg(MISCREG_LDTR_LIMIT, 0xffff);
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tc->setMiscReg(MISCREG_LDTR_ATTR, 0);
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tc->setMiscReg(MISCREG_TR, 0);
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tc->setMiscReg(MISCREG_TR_BASE, 0);
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tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
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tc->setMiscReg(MISCREG_TR_ATTR, 0);
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// This value should be the family/model/stepping of the processor.
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// (page 418). It should be consistent with the value from CPUID, but the
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// actual value probably doesn't matter much.
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tc->setIntReg(INTREG_RDX, 0);
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// TODO initialize x87, 64 bit, and 128 bit media state
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tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
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for (int i = 0; i < 8; i++) {
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tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
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tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
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}
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tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0);
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tc->setMiscReg(MISCREG_DEF_TYPE, 0);
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tc->setMiscReg(MISCREG_MCG_CAP, 0x104);
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tc->setMiscReg(MISCREG_MCG_STATUS, 0);
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tc->setMiscReg(MISCREG_MCG_CTL, 0);
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for (int i = 0; i < 5; i++) {
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tc->setMiscReg(MISCREG_MC_CTL(i), 0);
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tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
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tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
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tc->setMiscReg(MISCREG_MC_MISC(i), 0);
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}
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tc->setMiscReg(MISCREG_DR0, 0);
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tc->setMiscReg(MISCREG_DR1, 0);
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tc->setMiscReg(MISCREG_DR2, 0);
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tc->setMiscReg(MISCREG_DR3, 0);
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tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0);
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tc->setMiscReg(MISCREG_DR7, 0x0000000000000400);
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tc->setMiscReg(MISCREG_TSC, 0);
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tc->setMiscReg(MISCREG_TSC_AUX, 0);
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for (int i = 0; i < 4; i++) {
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tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
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tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
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}
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tc->setMiscReg(MISCREG_STAR, 0);
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tc->setMiscReg(MISCREG_LSTAR, 0);
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tc->setMiscReg(MISCREG_CSTAR, 0);
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tc->setMiscReg(MISCREG_SF_MASK, 0);
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tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0);
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tc->setMiscReg(MISCREG_SYSENTER_CS, 0);
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tc->setMiscReg(MISCREG_SYSENTER_ESP, 0);
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tc->setMiscReg(MISCREG_SYSENTER_EIP, 0);
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tc->setMiscReg(MISCREG_PAT, 0x0007040600070406);
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tc->setMiscReg(MISCREG_SYSCFG, 0x20601);
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tc->setMiscReg(MISCREG_IORR_BASE0, 0);
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tc->setMiscReg(MISCREG_IORR_BASE1, 0);
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tc->setMiscReg(MISCREG_IORR_MASK0, 0);
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tc->setMiscReg(MISCREG_IORR_MASK1, 0);
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tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000);
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tc->setMiscReg(MISCREG_TOP_MEM2, 0x0);
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tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0);
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tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0);
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tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0);
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tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0);
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tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0);
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// Invalidate the caches (this should already be done for us)
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// TODO Turn on the APIC. This should be handled elsewhere but it isn't
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// currently being handled at all.
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// TODO Set the SMRAM base address (SMBASE) to 0x00030000
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tc->setMiscReg(MISCREG_VM_CR, 0);
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tc->setMiscReg(MISCREG_IGNNE, 0);
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tc->setMiscReg(MISCREG_SMM_CTL, 0);
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tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
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}
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#endif
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void startupCPU(ThreadContext *tc, int cpuId)
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{
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if (cpuId == 0) {
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// This is the boot strap processor (BSP). Initialize it to look like
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// the boot loader has just turned control over to the 64 bit OS.
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// Enable paging, turn on long mode, etc.
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tc->activate(0);
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} else {
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// This is an application processor (AP). It should be initialized to
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// look like only the BIOS POST has run on it and put then put it into
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// a halted state.
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}
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}
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} //namespace X86_ISA
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