502ad1e675
PciDev and IntDev stuck out as the only device classes that ended in 'Dev' rather than 'Device'. This patch takes care of that inconsistency. Note that you may need to delete pre-existing files matching build/*/python/m5/internal/param_* as scons does not pick up indirect dependencies on imported python modules when generating params, and the PciDev -> PciDevice rename takes place in a file (dev/Device.py) that gets imported quite a bit. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
312 lines
8.4 KiB
C++
312 lines
8.4 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Andreas Hansson
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*/
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#ifndef __ARCH_X86_INTERRUPTS_HH__
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#define __ARCH_X86_INTERRUPTS_HH__
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#include "arch/x86/regs/apic.hh"
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#include "arch/x86/faults.hh"
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#include "arch/x86/intmessage.hh"
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#include "base/bitfield.hh"
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#include "cpu/thread_context.hh"
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#include "dev/x86/intdev.hh"
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#include "dev/io_device.hh"
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#include "params/X86LocalApic.hh"
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#include "sim/eventq.hh"
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class ThreadContext;
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class BaseCPU;
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int divideFromConf(uint32_t conf);
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namespace X86ISA {
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ApicRegIndex decodeAddr(Addr paddr);
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class Interrupts : public BasicPioDevice, IntDevice
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{
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protected:
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// Storage for the APIC registers
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uint32_t regs[NUM_APIC_REGS];
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BitUnion32(LVTEntry)
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Bitfield<7, 0> vector;
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Bitfield<10, 8> deliveryMode;
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Bitfield<12> status;
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Bitfield<13> polarity;
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Bitfield<14> remoteIRR;
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Bitfield<15> trigger;
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Bitfield<16> masked;
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Bitfield<17> periodic;
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EndBitUnion(LVTEntry)
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/*
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* Timing related stuff.
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*/
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class ApicTimerEvent : public Event
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{
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private:
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Interrupts *localApic;
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public:
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ApicTimerEvent(Interrupts *_localApic) :
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Event(), localApic(_localApic)
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{}
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void process()
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{
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assert(localApic);
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if (localApic->triggerTimerInterrupt()) {
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localApic->setReg(APIC_INITIAL_COUNT,
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localApic->readReg(APIC_INITIAL_COUNT));
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}
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}
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};
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ApicTimerEvent apicTimerEvent;
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/*
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* A set of variables to keep track of interrupts that don't go through
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* the IRR.
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*/
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bool pendingSmi;
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uint8_t smiVector;
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bool pendingNmi;
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uint8_t nmiVector;
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bool pendingExtInt;
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uint8_t extIntVector;
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bool pendingInit;
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uint8_t initVector;
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bool pendingStartup;
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uint8_t startupVector;
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bool startedUp;
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// This is a quick check whether any of the above (except ExtInt) are set.
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bool pendingUnmaskableInt;
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// A count of how many IPIs are in flight.
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int pendingIPIs;
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/*
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* IRR and ISR maintenance.
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*/
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uint8_t IRRV;
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uint8_t ISRV;
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int
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findRegArrayMSB(ApicRegIndex base)
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{
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int offset = 7;
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do {
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if (regs[base + offset] != 0) {
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return offset * 32 + findMsbSet(regs[base + offset]);
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}
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} while (offset--);
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return 0;
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}
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void
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updateIRRV()
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{
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IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
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}
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void
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updateISRV()
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{
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ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
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}
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void
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setRegArrayBit(ApicRegIndex base, uint8_t vector)
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{
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regs[base + (vector / 32)] |= (1 << (vector % 32));
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}
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void
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clearRegArrayBit(ApicRegIndex base, uint8_t vector)
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{
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regs[base + (vector / 32)] &= ~(1 << (vector % 32));
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}
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bool
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getRegArrayBit(ApicRegIndex base, uint8_t vector)
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{
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return bits(regs[base + (vector / 32)], vector % 5);
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}
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void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
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BaseCPU *cpu;
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int initialApicId;
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// Port for receiving interrupts
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IntSlavePort intSlavePort;
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public:
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int getInitialApicId() { return initialApicId; }
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/*
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* Params stuff.
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*/
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typedef X86LocalApicParams Params;
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void setCPU(BaseCPU * newCPU);
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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/*
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* Initialize this object by registering it with the IO APIC.
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*/
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void init();
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/*
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* Functions to interact with the interrupt port from IntDevice.
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*/
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Tick read(PacketPtr pkt);
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Tick write(PacketPtr pkt);
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Tick recvMessage(PacketPtr pkt);
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Tick recvResponse(PacketPtr pkt);
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bool
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triggerTimerInterrupt()
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{
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LVTEntry entry = regs[APIC_LVT_TIMER];
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if (!entry.masked)
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requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
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return entry.periodic;
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}
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AddrRangeList getIntAddrRange() const;
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BaseMasterPort &getMasterPort(const std::string &if_name,
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PortID idx = InvalidPortID)
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{
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if (if_name == "int_master") {
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return intMasterPort;
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}
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return BasicPioDevice::getMasterPort(if_name, idx);
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}
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BaseSlavePort &getSlavePort(const std::string &if_name,
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PortID idx = InvalidPortID)
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{
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if (if_name == "int_slave") {
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return intSlavePort;
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}
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return BasicPioDevice::getSlavePort(if_name, idx);
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}
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/*
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* Functions to access and manipulate the APIC's registers.
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*/
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uint32_t readReg(ApicRegIndex miscReg);
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void setReg(ApicRegIndex reg, uint32_t val);
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void
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setRegNoEffect(ApicRegIndex reg, uint32_t val)
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{
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regs[reg] = val;
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}
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/*
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* Constructor.
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*/
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Interrupts(Params * p);
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/*
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* Functions for retrieving interrupts for the CPU to handle.
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*/
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bool checkInterrupts(ThreadContext *tc) const;
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Fault getInterrupt(ThreadContext *tc);
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void updateIntrInfo(ThreadContext *tc);
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/*
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* Serialization.
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*/
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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/*
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* Old functions needed for compatability but which will be phased out
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* eventually.
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*/
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void
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post(int int_num, int index)
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{
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panic("Interrupts::post unimplemented!\n");
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}
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void
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clear(int int_num, int index)
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{
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panic("Interrupts::clear unimplemented!\n");
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}
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void
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clearAll()
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{
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panic("Interrupts::clearAll unimplemented!\n");
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}
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};
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} // namespace X86ISA
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#endif // __ARCH_X86_INTERRUPTS_HH__
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