b64eae5e52
SConscript: Added more files to compile: dev/pcifake.cc, dev/isa_fake.cc, kern/freebsd/freebsd_system.cc, kern/freebsd/freebsd_events.cc. arch/alpha/isa_traits.hh: Added constant for argument register 2 as it is needed by FreebsdSystem::doCalibrateClocks(). cpu/exec_context.hh: cpu/o3/alpha_cpu.hh: Replaced htoa()s with gtoh() and htog(). cpu/o3/fetch_impl.hh: cpu/simple/cpu.cc: Replaced htoa() with gtoh(). dev/disk_image.cc: Replaced htoa()s with letoh()s. dev/ide_ctrl.cc: Got rid of magic numbers. Added IdeChannel and IdeRegType type names where necessary. dev/ide_ctrl.hh: Got rid of unnecessary macros. Changed RegType_t to IdeRegType. Changed bmi_regs to allow accessing registers by name instead of just by array index. Added IdeChannel enum type to use in place of bool variables which were used to specify IDE channel. dev/ide_disk.cc: Rewrote IdeDisk::read and IdeDisk::write functions to specify registers by name instead of indexing through an array. dev/ide_disk.hh: Updated command register struct. dev/ns_gige.cc: dev/ns_gige.hh: Made ReadConfig and WriteConfig begin with a lower-case letter. writeConfig() now takes a pointer to data as a parameter instead of a copy of data. dev/pciconfigall.cc: writeConfig() now takes a pointer to data as a parameter instead of a copy of data. dev/pcidev.cc: Cleaned up readConfig() and writeConfig() functions. dev/pcidev.hh: Added macros to make code that works with the BARs (base adress registers) more readable. writeConfig() now takes a pointer to data. dev/pcireg.h: Changed PCIConfig struct to make accessing elements more straight forward. Removed type 1 (for PCI-to-PCI bridges) PCI configuration space struct since it is not used. dev/rtcreg.h: Added macros for bit fields in RTC status registers A & B. dev/sinic.cc: Function name change: WriteConfig --> writeConfig. writeConfig() now takes a pointer to data instead of a copy of data. The accessing of elements of PCIConfig structure is updated. dev/sinic.hh: Function name change: WriteConfig --> writeConfig. writeConfig() now takes a pointer to data instead of a copy of data. dev/tsunami_io.cc: Added implementation of new RTC and PIT classes. dev/tsunami_io.hh: Added classes for RTC and PIT modules. dev/tsunamireg.h: Added macros for DMA ports used by Tsunami-Tru64. dev/uart8250.cc: Got rid of a magic number. Transmit (Tx) interrupts should clear upon a read of the Interrupt ID register. dev/uart8250.hh: Added comments and macros dealing with the UART Interrupt ID register. kern/linux/linux_system.cc: Replaced htoa() with htog(). python/m5/objects/Pci.py: PciFake is a python class for Pci Devices that do nothing. python/m5/objects/Tsunami.py: TsunamiFake was renamed as IsaFake. sim/system.cc: Replaced htoa()s with htog()s. dev/isa_fake.cc: New BitKeeper file ``dev/isa_fake.cc'' TsunamiFake was renamed as IsaFake. dev/isa_fake.hh: New BitKeeper file ``dev/isa_fake.hh'' TsunmaiFake was renamed as IsaFake. dev/pitreg.h: New BitKeeper file ``dev/pitreg.h'' Useful macros for working with PIT (Periodic Interval Timer) registers. --HG-- extra : convert_revision : 33f3a8a1034af4f6c71b32dd743e371c8613e780
748 lines
20 KiB
C++
748 lines
20 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* Tsunami I/O including PIC, PIT, RTC, DMA
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*/
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#include <sys/time.h>
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "dev/tsunami_io.hh"
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#include "dev/tsunami.hh"
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#include "dev/pitreg.h"
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "sim/builder.hh"
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#include "dev/tsunami_cchip.hh"
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#include "dev/tsunamireg.h"
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#include "dev/rtcreg.h"
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#include "mem/functional/memory_control.hh"
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using namespace std;
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TsunamiIO::RTC::RTC(Tsunami* t, Tick i)
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: SimObject("RTC"), event(t, i), addr(0)
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{
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memset(clock_data, 0, sizeof(clock_data));
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stat_regA = RTCA_32768HZ | RTCA_1024HZ;
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stat_regB = RTCB_PRDC_IE |RTCB_BIN | RTCB_24HR;
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}
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void
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TsunamiIO::RTC::set_time(time_t t)
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{
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struct tm tm;
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gmtime_r(&t, &tm);
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sec = tm.tm_sec;
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min = tm.tm_min;
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hour = tm.tm_hour;
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wday = tm.tm_wday + 1;
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mday = tm.tm_mday;
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mon = tm.tm_mon + 1;
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year = tm.tm_year;
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DPRINTFN("Real-time clock set to %s", asctime(&tm));
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}
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void
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TsunamiIO::RTC::writeAddr(const uint8_t *data)
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{
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if (*data <= RTC_STAT_REGD)
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addr = *data;
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else
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panic("RTC addresses over 0xD are not implemented.\n");
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}
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void
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TsunamiIO::RTC::writeData(const uint8_t *data)
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{
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if (addr < RTC_STAT_REGA)
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clock_data[addr] = *data;
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else {
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switch (addr) {
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case RTC_STAT_REGA:
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if (*data != (RTCA_32768HZ | RTCA_1024HZ))
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panic("Unimplemented RTC register A value write!\n");
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stat_regA = *data;
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break;
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case RTC_STAT_REGB:
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if ((*data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != (RTCB_BIN | RTCB_24HR))
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panic("Write to RTC reg B bits that are not implemented!\n");
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if (*data & RTCB_PRDC_IE) {
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if (!event.scheduled())
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event.scheduleIntr();
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} else {
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if (event.scheduled())
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event.deschedule();
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}
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stat_regB = *data;
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break;
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case RTC_STAT_REGC:
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case RTC_STAT_REGD:
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panic("RTC status registers C and D are not implemented.\n");
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break;
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}
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}
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}
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void
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TsunamiIO::RTC::readData(uint8_t *data)
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{
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if (addr < RTC_STAT_REGA)
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*data = clock_data[addr];
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else {
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switch (addr) {
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case RTC_STAT_REGA:
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// toggle UIP bit for linux
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stat_regA ^= RTCA_UIP;
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*data = stat_regA;
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break;
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case RTC_STAT_REGB:
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*data = stat_regB;
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break;
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case RTC_STAT_REGC:
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case RTC_STAT_REGD:
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*data = 0x00;
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break;
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}
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}
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}
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void
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TsunamiIO::RTC::serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(addr);
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SERIALIZE_ARRAY(clock_data, sizeof(clock_data));
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SERIALIZE_SCALAR(stat_regA);
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SERIALIZE_SCALAR(stat_regB);
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// serialize the RTC event
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nameOut(os, csprintf("%s.event", name()));
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event.serialize(os);
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}
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void
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TsunamiIO::RTC::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(addr);
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UNSERIALIZE_ARRAY(clock_data, sizeof(clock_data));
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UNSERIALIZE_SCALAR(stat_regA);
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UNSERIALIZE_SCALAR(stat_regB);
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// unserialze the event
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event.unserialize(cp, csprintf("%s.event", section));
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}
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TsunamiIO::RTC::RTCEvent::RTCEvent(Tsunami*t, Tick i)
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: Event(&mainEventQueue), tsunami(t), interval(i)
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{
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DPRINTF(MC146818, "RTC Event Initilizing\n");
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schedule(curTick + interval);
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}
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void
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TsunamiIO::RTC::RTCEvent::scheduleIntr()
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{
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schedule(curTick + interval);
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}
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void
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TsunamiIO::RTC::RTCEvent::process()
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{
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DPRINTF(MC146818, "RTC Timer Interrupt\n");
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schedule(curTick + interval);
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//Actually interrupt the processor here
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tsunami->cchip->postRTC();
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}
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const char *
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TsunamiIO::RTC::RTCEvent::description()
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{
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return "tsunami RTC interrupt";
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}
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void
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TsunamiIO::RTC::RTCEvent::serialize(std::ostream &os)
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{
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Tick time = when();
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SERIALIZE_SCALAR(time);
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}
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void
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TsunamiIO::RTC::RTCEvent::unserialize(Checkpoint *cp, const std::string §ion)
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{
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Tick time;
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UNSERIALIZE_SCALAR(time);
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reschedule(time);
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}
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TsunamiIO::PITimer::PITimer()
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: SimObject("PITimer"), counter0(counter[0]), counter1(counter[1]),
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counter2(counter[2])
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{
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}
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void
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TsunamiIO::PITimer::writeControl(const uint8_t *data)
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{
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int rw;
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int sel;
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sel = GET_CTRL_SEL(*data);
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if (sel == PIT_READ_BACK)
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panic("PITimer Read-Back Command is not implemented.\n");
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rw = GET_CTRL_RW(*data);
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if (rw == PIT_RW_LATCH_COMMAND)
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counter[sel].latchCount();
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else {
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counter[sel].setRW(rw);
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counter[sel].setMode(GET_CTRL_MODE(*data));
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counter[sel].setBCD(GET_CTRL_BCD(*data));
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}
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}
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void
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TsunamiIO::PITimer::serialize(std::ostream &os)
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{
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// serialize the counters
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nameOut(os, csprintf("%s.counter0", name()));
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counter0.serialize(os);
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nameOut(os, csprintf("%s.counter1", name()));
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counter1.serialize(os);
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nameOut(os, csprintf("%s.counter2", name()));
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counter2.serialize(os);
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}
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void
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TsunamiIO::PITimer::unserialize(Checkpoint *cp, const std::string §ion)
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{
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// unserialze the counters
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counter0.unserialize(cp, csprintf("%s.counter0", section));
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counter1.unserialize(cp, csprintf("%s.counter1", section));
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counter2.unserialize(cp, csprintf("%s.counter2", section));
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}
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TsunamiIO::PITimer::Counter::Counter()
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: SimObject("Counter"), event(this), count(0), latched_count(0), period(0),
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mode(0), output_high(false), latch_on(false), read_byte(LSB),
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write_byte(LSB)
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{
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}
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void
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TsunamiIO::PITimer::Counter::latchCount()
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{
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// behave like a real latch
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if(!latch_on) {
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latch_on = true;
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read_byte = LSB;
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latched_count = count;
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}
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}
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void
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TsunamiIO::PITimer::Counter::read(uint8_t *data)
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{
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if (latch_on) {
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switch (read_byte) {
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case LSB:
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read_byte = MSB;
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*data = (uint8_t)latched_count;
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break;
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case MSB:
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read_byte = LSB;
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latch_on = false;
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*data = latched_count >> 8;
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break;
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}
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} else {
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switch (read_byte) {
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case LSB:
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read_byte = MSB;
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*data = (uint8_t)count;
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break;
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case MSB:
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read_byte = LSB;
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*data = count >> 8;
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break;
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}
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}
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}
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void
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TsunamiIO::PITimer::Counter::write(const uint8_t *data)
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{
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switch (write_byte) {
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case LSB:
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count = (count & 0xFF00) | *data;
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if (event.scheduled())
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event.deschedule();
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output_high = false;
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write_byte = MSB;
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break;
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case MSB:
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count = (count & 0x00FF) | (*data << 8);
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period = count;
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if (period > 0) {
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DPRINTF(Tsunami, "Timer set to curTick + %d\n", count * event.interval);
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event.schedule(curTick + count * event.interval);
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}
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write_byte = LSB;
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break;
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}
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}
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void
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TsunamiIO::PITimer::Counter::setRW(int rw_val)
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{
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if (rw_val != PIT_RW_16BIT)
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panic("Only LSB/MSB read/write is implemented.\n");
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}
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void
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TsunamiIO::PITimer::Counter::setMode(int mode_val)
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{
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if(mode_val != PIT_MODE_INTTC && mode_val != PIT_MODE_RATEGEN &&
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mode_val != PIT_MODE_SQWAVE)
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panic("PIT mode %#x is not implemented: \n", mode_val);
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mode = mode_val;
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}
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void
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TsunamiIO::PITimer::Counter::setBCD(int bcd_val)
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{
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if (bcd_val != PIT_BCD_FALSE)
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panic("PITimer does not implement BCD counts.\n");
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}
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bool
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TsunamiIO::PITimer::Counter::outputHigh()
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{
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return output_high;
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}
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void
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TsunamiIO::PITimer::Counter::serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(count);
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SERIALIZE_SCALAR(latched_count);
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SERIALIZE_SCALAR(period);
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SERIALIZE_SCALAR(mode);
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SERIALIZE_SCALAR(output_high);
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SERIALIZE_SCALAR(latch_on);
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SERIALIZE_SCALAR(read_byte);
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SERIALIZE_SCALAR(write_byte);
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// serialize the counter event
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nameOut(os, csprintf("%s.event", name()));
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event.serialize(os);
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}
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void
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TsunamiIO::PITimer::Counter::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(count);
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UNSERIALIZE_SCALAR(latched_count);
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UNSERIALIZE_SCALAR(period);
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UNSERIALIZE_SCALAR(mode);
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UNSERIALIZE_SCALAR(output_high);
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UNSERIALIZE_SCALAR(latch_on);
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UNSERIALIZE_SCALAR(read_byte);
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UNSERIALIZE_SCALAR(write_byte);
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// unserialze the counter event
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event.unserialize(cp, csprintf("%s.event", section));
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}
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TsunamiIO::PITimer::Counter::CounterEvent::CounterEvent(Counter* c_ptr)
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: Event(&mainEventQueue)
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{
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interval = (Tick)(Clock::Float::s / 1193180.0);
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counter = c_ptr;
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}
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void
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TsunamiIO::PITimer::Counter::CounterEvent::process()
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{
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DPRINTF(Tsunami, "Timer Interrupt\n");
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switch (counter->mode) {
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case PIT_MODE_INTTC:
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counter->output_high = true;
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case PIT_MODE_RATEGEN:
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case PIT_MODE_SQWAVE:
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break;
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default:
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panic("Unimplemented PITimer mode.\n");
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}
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}
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const char *
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TsunamiIO::PITimer::Counter::CounterEvent::description()
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{
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return "tsunami 8254 Interval timer";
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}
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void
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TsunamiIO::PITimer::Counter::CounterEvent::serialize(std::ostream &os)
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{
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Tick time = scheduled() ? when() : 0;
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SERIALIZE_SCALAR(time);
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SERIALIZE_SCALAR(interval);
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}
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void
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TsunamiIO::PITimer::Counter::CounterEvent::unserialize(Checkpoint *cp, const std::string §ion)
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{
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Tick time;
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UNSERIALIZE_SCALAR(time);
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UNSERIALIZE_SCALAR(interval);
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if (time)
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schedule(time);
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}
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TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
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Addr a, MemoryController *mmu, HierParams *hier, Bus *bus,
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Tick pio_latency, Tick ci)
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: PioDevice(name, t), addr(a), clockInterval(ci), tsunami(t), rtc(t, ci)
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{
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mmu->add_child(this, RangeSize(addr, size));
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if (bus) {
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pioInterface = newPioInterface(name, hier, bus, this,
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&TsunamiIO::cacheAccess);
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pioInterface->addAddrRange(RangeSize(addr, size));
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pioLatency = pio_latency * bus->clockRate;
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}
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// set the back pointer from tsunami to myself
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tsunami->io = this;
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timerData = 0;
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rtc.set_time(init_time == 0 ? time(NULL) : init_time);
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picr = 0;
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picInterrupting = false;
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}
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Tick
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TsunamiIO::frequency() const
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{
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return Clock::Frequency / clockInterval;
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}
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Fault
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TsunamiIO::read(MemReqPtr &req, uint8_t *data)
|
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{
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DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n",
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req->vaddr, req->size, req->vaddr & 0xfff);
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|
|
Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
|
|
|
|
|
|
switch(req->size) {
|
|
case sizeof(uint8_t):
|
|
switch(daddr) {
|
|
// PIC1 mask read
|
|
case TSDEV_PIC1_MASK:
|
|
*(uint8_t*)data = ~mask1;
|
|
return No_Fault;
|
|
case TSDEV_PIC2_MASK:
|
|
*(uint8_t*)data = ~mask2;
|
|
return No_Fault;
|
|
case TSDEV_PIC1_ISR:
|
|
// !!! If this is modified 64bit case needs to be too
|
|
// Pal code has to do a 64 bit physical read because there is
|
|
// no load physical byte instruction
|
|
*(uint8_t*)data = picr;
|
|
return No_Fault;
|
|
case TSDEV_PIC2_ISR:
|
|
// PIC2 not implemnted... just return 0
|
|
*(uint8_t*)data = 0x00;
|
|
return No_Fault;
|
|
case TSDEV_TMR0_DATA:
|
|
pitimer.counter0.read(data);
|
|
return No_Fault;
|
|
case TSDEV_TMR1_DATA:
|
|
pitimer.counter1.read(data);
|
|
return No_Fault;
|
|
case TSDEV_TMR2_DATA:
|
|
pitimer.counter2.read(data);
|
|
return No_Fault;
|
|
case TSDEV_RTC_DATA:
|
|
rtc.readData(data);
|
|
return No_Fault;
|
|
case TSDEV_CTRL_PORTB:
|
|
if (pitimer.counter2.outputHigh())
|
|
*data = PORTB_SPKR_HIGH;
|
|
else
|
|
*data = 0x00;
|
|
return No_Fault;
|
|
default:
|
|
panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
|
|
}
|
|
case sizeof(uint16_t):
|
|
case sizeof(uint32_t):
|
|
panic("I/O Read - invalid size - va %#x size %d\n",
|
|
req->vaddr, req->size);
|
|
|
|
case sizeof(uint64_t):
|
|
switch(daddr) {
|
|
case TSDEV_PIC1_ISR:
|
|
// !!! If this is modified 8bit case needs to be too
|
|
// Pal code has to do a 64 bit physical read because there is
|
|
// no load physical byte instruction
|
|
*(uint64_t*)data = (uint64_t)picr;
|
|
return No_Fault;
|
|
default:
|
|
panic("I/O Read - invalid size - va %#x size %d\n",
|
|
req->vaddr, req->size);
|
|
}
|
|
|
|
default:
|
|
panic("I/O Read - invalid size - va %#x size %d\n",
|
|
req->vaddr, req->size);
|
|
}
|
|
panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
|
|
|
|
return No_Fault;
|
|
}
|
|
|
|
Fault
|
|
TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
|
|
{
|
|
|
|
#if TRACING_ON
|
|
uint8_t dt = *(uint8_t*)data;
|
|
uint64_t dt64 = dt;
|
|
#endif
|
|
|
|
DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
|
|
req->vaddr, req->size, req->vaddr & 0xfff, dt64);
|
|
|
|
Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
|
|
|
|
switch(req->size) {
|
|
case sizeof(uint8_t):
|
|
switch(daddr) {
|
|
case TSDEV_PIC1_MASK:
|
|
mask1 = ~(*(uint8_t*)data);
|
|
if ((picr & mask1) && !picInterrupting) {
|
|
picInterrupting = true;
|
|
tsunami->cchip->postDRIR(55);
|
|
DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
|
|
}
|
|
if ((!(picr & mask1)) && picInterrupting) {
|
|
picInterrupting = false;
|
|
tsunami->cchip->clearDRIR(55);
|
|
DPRINTF(Tsunami, "clearing pic interrupt\n");
|
|
}
|
|
return No_Fault;
|
|
case TSDEV_PIC2_MASK:
|
|
mask2 = *(uint8_t*)data;
|
|
//PIC2 Not implemented to interrupt
|
|
return No_Fault;
|
|
case TSDEV_PIC1_ACK:
|
|
// clear the interrupt on the PIC
|
|
picr &= ~(1 << (*(uint8_t*)data & 0xF));
|
|
if (!(picr & mask1))
|
|
tsunami->cchip->clearDRIR(55);
|
|
return No_Fault;
|
|
case TSDEV_DMA1_CMND:
|
|
return No_Fault;
|
|
case TSDEV_DMA2_CMND:
|
|
return No_Fault;
|
|
case TSDEV_DMA1_MMASK:
|
|
return No_Fault;
|
|
case TSDEV_DMA2_MMASK:
|
|
return No_Fault;
|
|
case TSDEV_PIC2_ACK:
|
|
return No_Fault;
|
|
case TSDEV_DMA1_RESET:
|
|
return No_Fault;
|
|
case TSDEV_DMA2_RESET:
|
|
return No_Fault;
|
|
case TSDEV_DMA1_MODE:
|
|
mode1 = *(uint8_t*)data;
|
|
return No_Fault;
|
|
case TSDEV_DMA2_MODE:
|
|
mode2 = *(uint8_t*)data;
|
|
return No_Fault;
|
|
case TSDEV_DMA1_MASK:
|
|
case TSDEV_DMA2_MASK:
|
|
return No_Fault;
|
|
case TSDEV_TMR0_DATA:
|
|
pitimer.counter0.write(data);
|
|
return No_Fault;
|
|
case TSDEV_TMR1_DATA:
|
|
pitimer.counter1.write(data);
|
|
return No_Fault;
|
|
case TSDEV_TMR2_DATA:
|
|
pitimer.counter2.write(data);
|
|
return No_Fault;
|
|
case TSDEV_TMR_CTRL:
|
|
pitimer.writeControl(data);
|
|
return No_Fault;
|
|
case TSDEV_RTC_ADDR:
|
|
rtc.writeAddr(data);
|
|
return No_Fault;
|
|
case TSDEV_KBD:
|
|
return No_Fault;
|
|
case TSDEV_RTC_DATA:
|
|
rtc.writeData(data);
|
|
return No_Fault;
|
|
case TSDEV_CTRL_PORTB:
|
|
// System Control Port B not implemented
|
|
return No_Fault;
|
|
default:
|
|
panic("I/O Write - va%#x size %d data %#x\n", req->vaddr, req->size, (int)*data);
|
|
}
|
|
case sizeof(uint16_t):
|
|
case sizeof(uint32_t):
|
|
case sizeof(uint64_t):
|
|
default:
|
|
panic("I/O Write - invalid size - va %#x size %d\n",
|
|
req->vaddr, req->size);
|
|
}
|
|
|
|
|
|
return No_Fault;
|
|
}
|
|
|
|
void
|
|
TsunamiIO::postPIC(uint8_t bitvector)
|
|
{
|
|
//PIC2 Is not implemented, because nothing of interest there
|
|
picr |= bitvector;
|
|
if (picr & mask1) {
|
|
tsunami->cchip->postDRIR(55);
|
|
DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
|
|
}
|
|
}
|
|
|
|
void
|
|
TsunamiIO::clearPIC(uint8_t bitvector)
|
|
{
|
|
//PIC2 Is not implemented, because nothing of interest there
|
|
picr &= ~bitvector;
|
|
if (!(picr & mask1)) {
|
|
tsunami->cchip->clearDRIR(55);
|
|
DPRINTF(Tsunami, "clearing pic interrupt to cchip\n");
|
|
}
|
|
}
|
|
|
|
Tick
|
|
TsunamiIO::cacheAccess(MemReqPtr &req)
|
|
{
|
|
return curTick + pioLatency;
|
|
}
|
|
|
|
void
|
|
TsunamiIO::serialize(std::ostream &os)
|
|
{
|
|
SERIALIZE_SCALAR(timerData);
|
|
SERIALIZE_SCALAR(mask1);
|
|
SERIALIZE_SCALAR(mask2);
|
|
SERIALIZE_SCALAR(mode1);
|
|
SERIALIZE_SCALAR(mode2);
|
|
SERIALIZE_SCALAR(picr);
|
|
SERIALIZE_SCALAR(picInterrupting);
|
|
|
|
// Serialize the timers
|
|
nameOut(os, csprintf("%s.pitimer", name()));
|
|
pitimer.serialize(os);
|
|
nameOut(os, csprintf("%s.rtc", name()));
|
|
rtc.serialize(os);
|
|
}
|
|
|
|
void
|
|
TsunamiIO::unserialize(Checkpoint *cp, const std::string §ion)
|
|
{
|
|
UNSERIALIZE_SCALAR(timerData);
|
|
UNSERIALIZE_SCALAR(mask1);
|
|
UNSERIALIZE_SCALAR(mask2);
|
|
UNSERIALIZE_SCALAR(mode1);
|
|
UNSERIALIZE_SCALAR(mode2);
|
|
UNSERIALIZE_SCALAR(picr);
|
|
UNSERIALIZE_SCALAR(picInterrupting);
|
|
|
|
// Unserialize the timers
|
|
pitimer.unserialize(cp, csprintf("%s.pitimer", section));
|
|
rtc.unserialize(cp, csprintf("%s.rtc", section));
|
|
}
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
|
|
|
|
SimObjectParam<Tsunami *> tsunami;
|
|
Param<time_t> time;
|
|
SimObjectParam<MemoryController *> mmu;
|
|
Param<Addr> addr;
|
|
SimObjectParam<Bus*> io_bus;
|
|
Param<Tick> pio_latency;
|
|
SimObjectParam<HierParams *> hier;
|
|
Param<Tick> frequency;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
|
|
|
|
INIT_PARAM(tsunami, "Tsunami"),
|
|
INIT_PARAM(time, "System time to use (0 for actual time"),
|
|
INIT_PARAM(mmu, "Memory Controller"),
|
|
INIT_PARAM(addr, "Device Address"),
|
|
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
|
|
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
|
|
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams),
|
|
INIT_PARAM(frequency, "clock interrupt frequency")
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
|
|
|
|
CREATE_SIM_OBJECT(TsunamiIO)
|
|
{
|
|
return new TsunamiIO(getInstanceName(), tsunami, time, addr, mmu, hier,
|
|
io_bus, pio_latency, frequency);
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)
|