The current TLM bridge only provides a Slave Port that allows the gem5 world to send request to the SystemC world. This patch series refractors and cleans up the existing code, and adds a Master Port that allows the SystemC world to send requests to the gem5 world. This patch: * Add callbacks for the Gem5SimControl that are called at before and * after simulate() Reviewed at http://reviews.gem5.org/r/3799/ Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
129 lines
4.6 KiB
C++
129 lines
4.6 KiB
C++
/*
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* Copyright (c) 2015, University of Kaiserslautern
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* Copyright (c) 2016, Dresden University of Technology (TU Dresden)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Matthias Jung
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* Christian Menard
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*/
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#ifndef __SC_SIM_CONTROL_HH__
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#define __SC_SIM_CONTROL_HH__
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#include <tlm_utils/simple_target_socket.h>
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#include <systemc>
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#include <tlm>
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#include "sc_logger.hh"
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#include "sc_module.hh"
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#include "sim/cxx_manager.hh"
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#include "sim/system.hh"
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#include "sim_control_if.hh"
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namespace Gem5SystemC
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{
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/**
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* This is the central SystemC module that orchestrates the gem5 simulation.
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*
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* The module is responsible for loading the configuration file, setting up and
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* maintaining the event queues, as well as starting and ending the simulation.
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* While it is mandatory to have one instance of this class for running a gem5
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* simulation in SystemC, it is not allowed to have multiple instances!
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*/
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class Gem5SimControl : public Module, public Gem5SimControlInterface
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{
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protected:
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CxxConfigManager* config_manager;
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Gem5SystemC::Logger logger;
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Tick simulationEnd;
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/*
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* Keep track of the slave and master ports that are created by gem5
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* according to the config file.
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*/
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std::map<const std::string, SCSlavePort*> slavePorts;
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std::map<const std::string, SCMasterPort*> masterPorts;
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/// Pointer to a previously created instance.
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static Gem5SimControl* instance;
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/** A callback that is called from the run thread before gem5 simulation is
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* started.
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*
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* A derived class may use this to perform any additional initializations
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* prior simulation.
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*/
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virtual void beforeSimulate() {}
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/** A callback that is called from the run thread after gem5 simulation
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* completed.
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*
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* A derived class may use this to perform any additional tasks after gem5
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* exits. For instance, a derived class could use this to call sc_stop().
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*/
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virtual void afterSimulate() {}
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public:
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SC_HAS_PROCESS(Gem5SimControl);
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/**
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* Constructor.
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*
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* This class has a public constructor although the class is actually a
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* singleton. The public constructor is required to ensure compatibility
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* to external SystemC based tools. For the same reason, the constructor
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* parameters are basic types (int, string).
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*
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* @param configFile location of the gem5 configuration file
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* @param simulationEnd number of ticks to simulate
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* @param gem5DebugFlags a space separated list of gem5 debug flags to be
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* set, a prepended '-' clears the flag
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*/
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Gem5SimControl(sc_core::sc_module_name name,
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const std::string& configFile,
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uint64_t simulationEnd,
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const std::string& gem5DebugFlags);
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void registerSlavePort(const std::string& name, SCSlavePort* port);
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void registerMasterPort(const std::string& name, SCMasterPort* port);
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SCSlavePort* getSlavePort(const std::string& name) override;
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SCMasterPort* getMasterPort(const std::string& name) override;
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void end_of_elaboration();
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void run();
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};
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}
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#endif
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