4f9ead58ff
--HG-- extra : convert_revision : c4e66cd678313f7fe169787cb1bf3e45f114c4fd
165 lines
5.1 KiB
Text
165 lines
5.1 KiB
Text
////////////////////////////////////////////////////////////////////
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//
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// Privilege mode instructions
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//
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output header {{
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/**
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* Base class for privelege mode operations.
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*/
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class Priv : public SparcStaticInst
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{
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protected:
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// Constructor
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Priv(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
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SparcStaticInst(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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};
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/**
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* Base class for user mode "tick" access.
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*/
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class PrivTick : public SparcStaticInst
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{
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protected:
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// Constructor
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PrivTick(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass) :
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SparcStaticInst(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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};
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/**
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* Base class for privelege mode operations with immediates.
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*/
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class PrivImm : public Priv
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{
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protected:
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// Constructor
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PrivImm(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass) :
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Priv(mnem, _machInst, __opClass), imm(SIMM13)
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{
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}
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uint32_t imm;
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};
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/**
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* Base class for user mode "tick" access with immediates.
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*/
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class PrivTickImm : public PrivTick
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{
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protected:
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// Constructor
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PrivTickImm(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass) :
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PrivTick(mnem, _machInst, __opClass), imm(SIMM13)
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{
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}
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uint32_t imm;
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};
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}};
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output decoder {{
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std::string Priv::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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return "Privileged Instruction";
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}
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std::string PrivTick::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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return "Regular access to Tick";
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}
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}};
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def template PrivExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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%(op_decl)s;
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%(op_rd)s;
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//If the processor isn't in privileged mode, fault out right away
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if(!PstatePriv)
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return new PrivilegedOpcode
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%(code)s;
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%(op_wb)s;
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}
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}};
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def template PrivTickExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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%(op_decl)s;
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%(op_rd)s;
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//If the processor isn't in privileged mode, fault out right away
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if(!PstatePriv && TickNpt)
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return new PrivilegedAction
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%(code)s;
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%(op_wb)s;
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}
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}};
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// Primary format for integer operate instructions:
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def format Priv(code, *opt_flags) {{
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uses_imm = (code.find('Rs2_or_imm13') != -1)
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if uses_imm:
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orig_code = code
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code = re.sub(r'Rs2_or_imm13', 'Rs2', orig_code)
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imm_code = re.sub(r'Rs2_or_imm13(\.\w+)?', 'imm', orig_code)
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cblk = CodeBlock(code)
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iop = InstObjParams(name, Name, 'Priv', cblk, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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exec_output = PrivExecute.subst(iop)
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if uses_imm:
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imm_cblk = CodeBlock(imm_code)
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imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm', imm_cblk,
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opt_flags)
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header_output += BasicDeclare.subst(imm_iop)
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decoder_output += BasicConstructor.subst(imm_iop)
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exec_output += PrivExecute.subst(imm_iop)
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decode_block = ROrImmDecode.subst(iop)
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else:
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decode_block = BasicDecode.subst(iop)
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}};
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// Primary format for integer operate instructions:
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def format PrivTick(code, *opt_flags) {{
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uses_imm = (code.find('Rs2_or_imm13') != -1)
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if uses_imm:
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orig_code = code
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code = re.sub(r'Rs2_or_imm13', 'Rs2', orig_code)
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imm_code = re.sub(r'Rs2_or_imm13(\.\w+)?', 'imm', orig_code)
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cblk = CodeBlock(code)
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iop = InstObjParams(name, Name, 'PrivTick', cblk, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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exec_output = PrivTickExecute.subst(iop)
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if uses_imm:
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imm_cblk = CodeBlock(imm_code)
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imm_iop = InstObjParams(name, Name + 'Imm', 'PrivTickImm', imm_cblk,
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opt_flags)
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header_output += BasicDeclare.subst(imm_iop)
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decoder_output += BasicConstructor.subst(imm_iop)
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exec_output += PrivTickExecute.subst(imm_iop)
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decode_block = Rb2OrImmDecode.subst(iop)
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else:
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decode_block = BasicDecode.subst(iop)
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}};
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