353 lines
39 KiB
Text
353 lines
39 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.134277 # Number of seconds simulated
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sim_ticks 134276988000 # Number of ticks simulated
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final_tick 134276988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 2261546 # Simulator instruction rate (inst/s)
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host_op_rate 2261545 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 3437525661 # Simulator tick rate (ticks/s)
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host_mem_usage 217500 # Number of bytes of host memory used
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host_seconds 39.06 # Real time elapsed on the host
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sim_insts 88340673 # Number of instructions simulated
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sim_ops 88340673 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read 11121920 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 558272 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 7712384 # Number of bytes written to this memory
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system.physmem.num_reads 173780 # Number of read requests responded to by this memory
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system.physmem.num_writes 120506 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 82828191 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 4157615 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 57436379 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 140264570 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 20276638 # DTB read hits
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system.cpu.dtb.read_misses 90148 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 20366786 # DTB read accesses
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system.cpu.dtb.write_hits 14613377 # DTB write hits
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system.cpu.dtb.write_misses 7252 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 14620629 # DTB write accesses
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system.cpu.dtb.data_hits 34890015 # DTB hits
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system.cpu.dtb.data_misses 97400 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 34987415 # DTB accesses
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system.cpu.itb.fetch_hits 88438074 # ITB hits
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system.cpu.itb.fetch_misses 3934 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 88442008 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 4583 # Number of system calls
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system.cpu.numCycles 268553976 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 88340673 # Number of instructions committed
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system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
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system.cpu.num_func_calls 3321606 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
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system.cpu.num_int_insts 78039444 # number of integer instructions
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system.cpu.num_fp_insts 267757 # number of float instructions
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system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
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system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
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system.cpu.num_mem_refs 34987415 # number of memory refs
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system.cpu.num_load_insts 20366786 # Number of load instructions
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system.cpu.num_store_insts 14620629 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 268553976 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 74391 # number of replacements
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system.cpu.icache.tagsinuse 1871.404551 # Cycle average of tags in use
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system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 1871.404551 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.913772 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.913772 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 88361638 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 88361638 # number of overall hits
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system.cpu.icache.overall_hits::total 88361638 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 76436 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 76436 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 76436 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses
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system.cpu.icache.overall_misses::total 76436 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 1436470000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 1436470000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 1436470000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 1436470000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 1436470000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 1436470000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 88438074 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 88438074 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 88438074 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000864 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18793.107960 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 18793.107960 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 18793.107960 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 76436 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 76436 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 76436 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1207162000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 1207162000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1207162000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 1207162000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1207162000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 1207162000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15793.107960 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15793.107960 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15793.107960 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 200248 # number of replacements
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system.cpu.dcache.tagsinuse 4078.858373 # Cycle average of tags in use
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system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 943232000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 4078.858373 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.995815 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.995815 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits
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system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits
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system.cpu.dcache.overall_hits::total 34685671 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses
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system.cpu.dcache.overall_misses::total 204344 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 2261000000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 2261000000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 7532210000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 7532210000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 9793210000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 9793210000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 9793210000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 9793210000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37208.307277 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52460.753040 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::cpu.data 47925.116470 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 47925.116470 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.writebacks::writebacks 161222 # number of writebacks
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system.cpu.dcache.writebacks::total 161222 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2078702000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 2078702000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7101476000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 7101476000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9180178000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 9180178000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9180178000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 9180178000 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
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system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34208.307277 # average ReadReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49460.753040 # average WriteReq mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44925.116470 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44925.116470 # average overall mshr miss latency
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 147405 # number of replacements
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system.cpu.l2cache.tagsinuse 18614.813333 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 122958 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 172748 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 0.711777 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::writebacks 15808.263557 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.inst 1305.254425 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 1501.295351 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::writebacks 0.482430 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.inst 0.039833 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.data 0.045816 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::total 0.568079 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 67713 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.data 27188 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 94901 # number of ReadReq hits
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system.cpu.l2cache.Writeback_hits::writebacks 161222 # number of Writeback hits
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system.cpu.l2cache.Writeback_hits::total 161222 # number of Writeback hits
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system.cpu.l2cache.ReadExReq_hits::cpu.data 12099 # number of ReadExReq hits
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system.cpu.l2cache.ReadExReq_hits::total 12099 # number of ReadExReq hits
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system.cpu.l2cache.demand_hits::cpu.inst 67713 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::cpu.data 39287 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::total 107000 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 67713 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 39287 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 107000 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 8723 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 33578 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 42301 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 131479 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 131479 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 8723 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 165057 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 173780 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 8723 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 165057 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 173780 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 453596000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1746056000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 2199652000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6836908000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 6836908000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 453596000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 8582964000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 9036560000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 453596000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 8582964000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 9036560000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 76436 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 60766 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 137202 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 161222 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 161222 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143578 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 143578 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 76436 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 204344 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 280780 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.114122 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.552579 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.915732 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.114122 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.807741 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.114122 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.807741 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 120506 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 120506 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8723 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33578 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 42301 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131479 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 131479 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 8723 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 165057 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 173780 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 8723 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 165057 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 173780 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 348920000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1343120000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1692040000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5259160000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5259160000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 348920000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6602280000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 6951200000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 348920000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6602280000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 6951200000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.552579 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.915732 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807741 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807741 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|