633 lines
71 KiB
Plaintext
633 lines
71 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.643030 # Number of seconds simulated
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sim_ticks 643030478500 # Number of ticks simulated
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final_tick 643030478500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 198283 # Simulator instruction rate (inst/s)
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host_op_rate 198283 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 69939236 # Simulator tick rate (ticks/s)
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host_mem_usage 217424 # Number of bytes of host memory used
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host_seconds 9194.13 # Real time elapsed on the host
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sim_insts 1823043370 # Number of instructions simulated
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sim_ops 1823043370 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read 94779264 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 185664 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 4281472 # Number of bytes written to this memory
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system.physmem.num_reads 1480926 # Number of read requests responded to by this memory
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system.physmem.num_writes 66898 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 147394668 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 288733 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 6658272 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 154052940 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 520282071 # DTB read hits
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system.cpu.dtb.read_misses 658976 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 520941047 # DTB read accesses
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system.cpu.dtb.write_hits 283837075 # DTB write hits
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system.cpu.dtb.write_misses 53680 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 283890755 # DTB write accesses
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system.cpu.dtb.data_hits 804119146 # DTB hits
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system.cpu.dtb.data_misses 712656 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 804831802 # DTB accesses
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system.cpu.itb.fetch_hits 398310361 # ITB hits
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system.cpu.itb.fetch_misses 225 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 398310586 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 39 # Number of system calls
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system.cpu.numCycles 1286060958 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 402586298 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 267183275 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 28898117 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 333702913 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 271687015 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 60998120 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 7269 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 415096525 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 3352093116 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 402586298 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 332685135 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 645195661 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 165271358 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 89752324 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 146 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 4176 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 398310361 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 11197226 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 1285935042 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.606736 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.132660 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 640739381 49.83% 49.83% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 57260959 4.45% 54.28% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 45174683 3.51% 57.79% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 73956325 5.75% 63.54% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 134643957 10.47% 74.01% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 43704830 3.40% 77.41% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 44948525 3.50% 80.91% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 8228368 0.64% 81.55% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 237278014 18.45% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 1285935042 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.313038 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.606481 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 451176980 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 71498937 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 618592802 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 8792068 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 135874255 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 30910962 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 12070 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 3252787569 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 45959 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 135874255 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 481268394 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 29024257 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 25510 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 595950971 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 43791655 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 3151351284 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 355 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 750555 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 36590752 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 2105050619 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 3698513195 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 3586317765 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 112195430 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 720081549 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 4177 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 82 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 124172087 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 732020123 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 345520616 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 66357929 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 8901879 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 2642218507 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 75 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 2155449111 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 17941201 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 818701684 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 780988431 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 36 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 1285935042 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.676173 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.767949 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 465245543 36.18% 36.18% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 229606292 17.86% 54.03% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 242969112 18.89% 72.93% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 129449912 10.07% 83.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 105111994 8.17% 91.17% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 71454382 5.56% 96.73% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 23774402 1.85% 98.58% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 15398679 1.20% 99.77% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 2924726 0.23% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 1285935042 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 19151 0.06% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 21356146 65.69% 65.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 11134345 34.25% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 1238361266 57.45% 57.45% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 16703 0.00% 57.45% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.45% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 27850917 1.29% 58.75% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 8254688 0.38% 59.13% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 7204646 0.33% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.46% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 584304865 27.11% 86.57% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 289453270 13.43% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::total 2155449111 # Type of FU issued
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system.cpu.iq.rate 1.676009 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 32509642 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.015083 # FU busy rate (busy events/executed inst)
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system.cpu.iq.int_inst_queue_reads 5498808910 # Number of integer instruction queue reads
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system.cpu.iq.int_inst_queue_writes 3382020905 # Number of integer instruction queue writes
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system.cpu.iq.int_inst_queue_wakeup_accesses 1990959088 # Number of integer instruction queue wakeup accesses
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system.cpu.iq.fp_inst_queue_reads 148475197 # Number of floating instruction queue reads
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system.cpu.iq.fp_inst_queue_writes 78969876 # Number of floating instruction queue writes
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system.cpu.iq.fp_inst_queue_wakeup_accesses 72622847 # Number of floating instruction queue wakeup accesses
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system.cpu.iq.int_alu_accesses 2112315501 # Number of integer alu accesses
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system.cpu.iq.fp_alu_accesses 75640500 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.forwLoads 67702370 # Number of loads that had data forwarded from stores
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
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system.cpu.iew.lsq.thread0.squashedLoads 220950097 # Number of loads squashed
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system.cpu.iew.lsq.thread0.ignoredResponses 171000 # Number of memory responses ignored because the instruction is squashed
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system.cpu.iew.lsq.thread0.memOrderViolation 71734 # Number of memory ordering violations
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system.cpu.iew.lsq.thread0.squashedStores 134725720 # Number of stores squashed
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system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
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system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
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system.cpu.iew.lsq.thread0.rescheduledLoads 4434 # Number of loads that were rescheduled
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system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 135874255 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 3818188 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 203306 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 3005431260 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 2750522 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 732020123 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 345520616 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 75 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 131111 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 4921 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 71734 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 30723187 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 903682 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 31626869 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 2066254472 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 520941220 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 89194639 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 363212678 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 804832688 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 279771397 # Number of branches executed
|
|
system.cpu.iew.exec_stores 283891468 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.606654 # Inst execution rate
|
|
system.cpu.iew.wb_sent 2065581707 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 2063581935 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1176945723 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 1742555439 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.604576 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.675414 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions
|
|
system.cpu.commit.commitCommittedOps 2008987604 # The number of committed instructions
|
|
system.cpu.commit.commitSquashedInsts 979738658 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 28886163 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 1150060787 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.746853 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.513737 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 543040951 47.22% 47.22% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 216685952 18.84% 66.06% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 119778809 10.41% 76.47% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 61132291 5.32% 81.79% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 44136002 3.84% 85.63% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 24968433 2.17% 87.80% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 19265020 1.68% 89.47% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 16055764 1.40% 90.87% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 104997565 9.13% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 1150060787 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 2008987604 # Number of instructions committed
|
|
system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 721864922 # Number of memory references committed
|
|
system.cpu.commit.loads 511070026 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 266706457 # Number of branches committed
|
|
system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 39955347 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 104997565 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 4028153074 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 6113513811 # The number of ROB writes
|
|
system.cpu.timesIdled 3507 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 125916 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.705447 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.705447 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.417540 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.417540 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 2630724063 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 1493026464 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 77824314 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 52830391 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.icache.replacements 8239 # number of replacements
|
|
system.cpu.icache.tagsinuse 1650.873085 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 398299261 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 9946 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 40046.175447 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 1650.873085 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.806090 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.806090 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 398299261 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 398299261 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 398299261 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 398299261 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 398299261 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 398299261 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 11100 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 11100 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 11100 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 11100 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 11100 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 11100 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 182477500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 182477500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 182477500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 182477500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 182477500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 182477500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 398310361 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 398310361 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 398310361 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 398310361 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 398310361 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 398310361 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000028 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000028 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000028 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16439.414414 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16439.414414 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16439.414414 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1153 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 1153 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 1153 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 1153 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 1153 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 1153 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9947 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 9947 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 9947 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 9947 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 9947 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 9947 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 119555000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 119555000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 119555000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 119555000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 119555000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 119555000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12019.201769 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12019.201769 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12019.201769 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 1527592 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4095.113983 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 660890207 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 1531688 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 431.478347 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 255376000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4095.113983 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999784 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999784 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 450646939 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 450646939 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 210243259 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 210243259 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 660890198 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 660890198 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 660890198 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 660890198 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1928305 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1928305 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 551637 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 551637 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2479942 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2479942 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2479942 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2479942 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 71444429000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 71444429000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20878144491 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 20878144491 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 59000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 59000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 92322573491 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 92322573491 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 92322573491 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 92322573491 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 452575244 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 452575244 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 663370140 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 663370140 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 663370140 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 663370140 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004261 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002617 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.003738 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.003738 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37050.377923 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37847.614448 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37227.714798 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37227.714798 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 79500 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 20500 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5678.571429 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 20500 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 107326 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 107326 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 468223 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 468223 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 480032 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 480032 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 948255 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 948255 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 948255 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 948255 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460082 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1460082 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71605 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 71605 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1531687 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1531687 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1531687 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1531687 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 49942277500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 49942277500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2493130000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2493130000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52435407500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 52435407500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52435407500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 52435407500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003226 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.090909 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002309 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002309 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34205.118274 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34817.819985 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35000 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34233.761532 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34233.761532 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 1480630 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 31935.913288 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 63583 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 1513317 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.042016 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 3059.437870 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 43.056925 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 28833.418493 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.093367 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.001314 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.879926 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.974607 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 7046 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 48913 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 55959 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 107326 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 107326 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 4750 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 4750 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 7046 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 53663 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 60709 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 7046 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 53663 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 60709 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2901 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 1411170 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 1414071 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 66855 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 66855 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2901 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 1478025 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 1480926 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2901 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 1478025 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 1480926 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 99564500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48413945500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 48513510000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2349021500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 2349021500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 99564500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 50762967000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 50862531500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 99564500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 50762967000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 50862531500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 9947 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1460083 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 1470030 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 107326 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 107326 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 71605 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 71605 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 9947 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1531688 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1541635 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 9947 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1531688 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1541635 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.291646 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.966500 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933664 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.291646 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964965 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.291646 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964965 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34320.751465 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34307.663499 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 35136.063122 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34320.751465 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34345.134216 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34320.751465 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34345.134216 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7500 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 66898 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 66898 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2901 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1411170 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1414071 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66855 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 66855 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2901 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 1478025 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 1480926 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2901 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 1478025 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 1480926 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 90197000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43747183500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43837380500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2147695000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2147695000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 90197000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45894878500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 45985075500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 90197000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45894878500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 45985075500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.291646 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.966500 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933664 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.291646 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964965 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.291646 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964965 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31091.692520 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31000.647335 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32124.672799 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31091.692520 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31051.489995 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31091.692520 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31051.489995 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|