sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
gem5/src/cpu
History
Andreas Hansson a8e6adb0b1 Atomic: Remove the physmem_port and access memory directly 
This patch removes the physmem_port from the Atomic CPU and instead
uses the system pointer to access the physmem when using the fastmem
option. The system already keeps track of the physmem and the valid
memory address ranges, and with this patch we merely make use of that
existing functionality. As a result of this change, the overloaded
getMasterPort in the Atomic CPU can be removed, thus unifying the CPUs.
2012-04-03 03:50:14 -04:00
..
checker MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
inorder MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
nocpu SCons: Support building without an ISA 2010-11-19 18:00:39 -06:00
o3 MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
ozone MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
pred BPred: Fix RAS to handle predicated call/return instructions. 2012-02-13 12:26:25 -06:00
simple Atomic: Remove the physmem_port and access memory directly 2012-04-03 03:50:14 -04:00
testers MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
trace includes: sort all includes 2011-04-15 10:44:06 -07:00
activity.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
activity.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
base.cc MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
base.hh Atomic: Remove the physmem_port and access memory directly 2012-04-03 03:50:14 -04:00
base_dyn_inst.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
base_dyn_inst_impl.hh CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable 2012-03-09 09:59:27 -05:00
BaseCPU.py CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable 2012-03-09 09:59:27 -05:00
CheckerCPU.py CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 2012-01-31 07:46:03 -08:00
cpuevent.cc Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00
cpuevent.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
decode.cc Decode: Pull instruction decoding out of the StaticInst class into its own. 2011-09-09 02:30:01 -07:00
decode.hh Decode: Pull instruction decoding out of the StaticInst class into its own. 2011-09-09 02:30:01 -07:00
decode_cache.hh Decode: Pull instruction decoding out of the StaticInst class into its own. 2011-09-09 02:30:01 -07:00
dummy_checker_builder.cc CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable 2012-03-09 09:59:27 -05:00
DummyChecker.py CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 2012-01-31 07:46:03 -08:00
exec_context.hh SE/FS: Expose the same methods on the CPUs in SE and FS modes. 2011-11-01 04:01:13 -07:00
exetrace.cc gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
exetrace.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
ExeTracer.py SimObjects: Clean up handling of C++ namespaces. 2008-10-09 22:19:39 -07:00
func_unit.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
func_unit.hh clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
FuncUnit.py CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. 2010-11-15 14:04:04 -06:00
inst_seq.hh build: fix compile problems pointed out by gcc 4.4 2009-11-04 16:57:01 -08:00
inteltrace.cc gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
inteltrace.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
IntelTrace.py SimObjects: Clean up handling of C++ namespaces. 2008-10-09 22:19:39 -07:00
intr_control.cc SE/FS: Get rid of FULL_SYSTEM in the CPU directory. 2011-11-18 01:33:28 -08:00
intr_control.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
IntrControl.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
legiontrace.cc Merge with main repository. 2012-01-07 02:10:34 -08:00
legiontrace.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
LegionTrace.py SimObjects: Clean up handling of C++ namespaces. 2008-10-09 22:19:39 -07:00
m5legion_interface.h add fsr to the list of registers we are interested in 2007-01-30 18:27:04 -05:00
nativetrace.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
nativetrace.hh clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
NativeTrace.py ARM: Make native trace print out what instruction caused an error. 2009-07-27 00:54:09 -07:00
op_class.hh CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. 2010-11-15 14:04:04 -06:00
pc_event.cc Merge yet again with the main repository. 2012-01-16 04:27:10 -08:00
pc_event.hh types: Move stuff for global types into src/base/types.hh 2009-05-17 14:34:50 -07:00
profile.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
profile.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
quiesce_event.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
quiesce_event.hh clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
SConscript CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable 2012-03-09 09:59:27 -05:00
simple_thread.cc SE/FS: Record the system pointer all the time for the simple CPU. 2012-02-10 02:05:31 -08:00
simple_thread.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
smt.hh includes: fix up code after sorting 2011-04-15 10:44:14 -07:00
static_inst.cc Decode: Pull instruction decoding out of the StaticInst class into its own. 2011-09-09 02:30:01 -07:00
static_inst.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
static_inst_fwd.hh StaticInst: Merge StaticInst and StaticInstBase. 2011-09-09 02:40:11 -07:00
thread_context.cc SE/FS: Make the functions available from the TC consistent between SE and FS. 2011-10-31 02:58:22 -07:00
thread_context.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
thread_state.cc CPU: Unify initMemProxies across CPUs and simulation modes 2012-03-30 09:38:35 -04:00
thread_state.hh CPU: Unify initMemProxies across CPUs and simulation modes 2012-03-30 09:38:35 -04:00
timebuf.hh Move sched_list.hh and timebuf.hh from src/base to src/cpu. 2011-01-03 14:35:47 -08:00
translation.hh Translation: Use a pointer type as the template argument. 2011-08-07 09:21:48 -07:00