a8e6adb0b1
This patch removes the physmem_port from the Atomic CPU and instead uses the system pointer to access the physmem when using the fastmem option. The system already keeps track of the physmem and the valid memory address ranges, and with this patch we merely make use of that existing functionality. As a result of this change, the overloaded getMasterPort in the Atomic CPU can be removed, thus unifying the CPUs.
198 lines
6.7 KiB
Python
198 lines
6.7 KiB
Python
# Copyright (c) 2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006-2008 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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# Simple test script
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#
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# "m5 test.py"
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import optparse
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import sys
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import m5
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from m5.defines import buildEnv
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from m5.objects import *
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from m5.util import addToPath, fatal
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addToPath('../common')
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addToPath('../ruby')
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import Options
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import Ruby
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import Simulation
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import CacheConfig
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from Caches import *
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from cpu2000 import *
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parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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Options.addSEOptions(parser)
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if '--ruby' in sys.argv:
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Ruby.define_options(parser)
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(options, args) = parser.parse_args()
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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multiprocesses = []
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apps = []
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if options.bench:
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apps = options.bench.split("-")
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if len(apps) != options.num_cpus:
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print "number of benchmarks not equal to set num_cpus!"
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sys.exit(1)
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for app in apps:
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try:
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if buildEnv['TARGET_ISA'] == 'alpha':
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exec("workload = %s('alpha', 'tru64', 'ref')" % app)
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else:
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exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app)
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multiprocesses.append(workload.makeLiveProcess())
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except:
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print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app)
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sys.exit(1)
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elif options.cmd:
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process = LiveProcess()
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process.executable = options.cmd
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process.cmd = [options.cmd] + options.options.split()
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multiprocesses.append(process)
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else:
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print >> sys.stderr, "No workload specified. Exiting!\n"
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sys.exit(1)
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if options.input != "":
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process.input = options.input
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if options.output != "":
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process.output = options.output
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if options.errout != "":
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process.errout = options.errout
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# By default, set workload to path of user-specified binary
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workloads = options.cmd
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numThreads = 1
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if options.cpu_type == "detailed" or options.cpu_type == "inorder":
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#check for SMT workload
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workloads = options.cmd.split(';')
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if len(workloads) > 1:
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process = []
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smt_idx = 0
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inputs = []
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outputs = []
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errouts = []
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if options.input != "":
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inputs = options.input.split(';')
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if options.output != "":
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outputs = options.output.split(';')
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if options.errout != "":
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errouts = options.errout.split(';')
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for wrkld in workloads:
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smt_process = LiveProcess()
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smt_process.executable = wrkld
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smt_process.cmd = wrkld + " " + options.options
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if inputs and inputs[smt_idx]:
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smt_process.input = inputs[smt_idx]
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if outputs and outputs[smt_idx]:
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smt_process.output = outputs[smt_idx]
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if errouts and errouts[smt_idx]:
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smt_process.errout = errouts[smt_idx]
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process += [smt_process, ]
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smt_idx += 1
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numThreads = len(workloads)
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(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
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CPUClass.clock = '2GHz'
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CPUClass.numThreads = numThreads;
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np = options.num_cpus
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system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
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physmem = PhysicalMemory(range=AddrRange("512MB")),
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membus = Bus(), mem_mode = test_mem_mode)
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# Sanity check
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if options.fastmem and (options.caches or options.l2cache):
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fatal("You cannot use fastmem in combination with caches!")
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for i in xrange(np):
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system.cpu[i].workload = multiprocesses[i]
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if options.fastmem:
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system.cpu[0].fastmem = True
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if options.checker:
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system.cpu[i].addCheckerCpu()
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if options.ruby:
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if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
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print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
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sys.exit(1)
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options.use_map = True
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Ruby.create_system(options, system)
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assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
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for i in xrange(np):
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ruby_port = system.ruby._cpu_ruby_ports[i]
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# Create the interrupt controller and connect its ports to Ruby
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system.cpu[i].createInterruptController()
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system.cpu[i].interrupts.pio = ruby_port.master
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system.cpu[i].interrupts.int_master = ruby_port.slave
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system.cpu[i].interrupts.int_slave = ruby_port.master
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# Connect the cpu's cache ports to Ruby
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system.cpu[i].icache_port = ruby_port.slave
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system.cpu[i].dcache_port = ruby_port.slave
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else:
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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CacheConfig.config_cache(options, system)
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root = Root(full_system = False, system = system)
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Simulation.run(options, root, system, FutureClass)
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