aad02f8088
Special mpy importer is gone; everything is just plain
Python now (funky, but straight-up).
May not completely work yet... generates identical ini
files for many configs/kernel settings, but I have yet
to run it against regressions. This commit is for my
own convenience and won't be pushed until more testing
is done.
python/m5/__init__.py:
Get rid of mpy_importer and param_types.
python/m5/config.py:
Major cleanup. We now have separate classes and
instances for SimObjects. Proxy handling and param
conversion significantly reorganized. No explicit
instantiation step anymore; we can dump an ini file
straight from the original tree.
Still needs more/better/truer comments.
test/genini.py:
Replace LoadMpyFile() with built-in execfile().
Export __main__.m5_build_env.
python/m5/objects/AlphaConsole.py:
python/m5/objects/AlphaFullCPU.py:
python/m5/objects/AlphaTLB.py:
python/m5/objects/BadDevice.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/CoherenceProtocol.py:
python/m5/objects/Device.py:
python/m5/objects/DiskImage.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Ide.py:
python/m5/objects/IntrControl.py:
python/m5/objects/MemTest.py:
python/m5/objects/Pci.py:
python/m5/objects/PhysicalMemory.py:
python/m5/objects/Platform.py:
python/m5/objects/Process.py:
python/m5/objects/Repl.py:
python/m5/objects/Root.py:
python/m5/objects/SimConsole.py:
python/m5/objects/SimpleDisk.py:
python/m5/objects/Tsunami.py:
python/m5/objects/Uart.py:
Fixes for eliminating mpy_importer, and modified
handling of frequency/latency params.
Also renamed parent to Parent.
--HG--
rename : python/m5/objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.py
rename : python/m5/objects/AlphaFullCPU.mpy => python/m5/objects/AlphaFullCPU.py
rename : python/m5/objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.py
rename : python/m5/objects/BadDevice.mpy => python/m5/objects/BadDevice.py
rename : python/m5/objects/BaseCPU.mpy => python/m5/objects/BaseCPU.py
rename : python/m5/objects/BaseCache.mpy => python/m5/objects/BaseCache.py
rename : python/m5/objects/BaseSystem.mpy => python/m5/objects/BaseSystem.py
rename : python/m5/objects/Bus.mpy => python/m5/objects/Bus.py
rename : python/m5/objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.py
rename : python/m5/objects/Device.mpy => python/m5/objects/Device.py
rename : python/m5/objects/DiskImage.mpy => python/m5/objects/DiskImage.py
rename : python/m5/objects/Ethernet.mpy => python/m5/objects/Ethernet.py
rename : python/m5/objects/Ide.mpy => python/m5/objects/Ide.py
rename : python/m5/objects/IntrControl.mpy => python/m5/objects/IntrControl.py
rename : python/m5/objects/MemTest.mpy => python/m5/objects/MemTest.py
rename : python/m5/objects/Pci.mpy => python/m5/objects/Pci.py
rename : python/m5/objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.py
rename : python/m5/objects/Platform.mpy => python/m5/objects/Platform.py
rename : python/m5/objects/Process.mpy => python/m5/objects/Process.py
rename : python/m5/objects/Repl.mpy => python/m5/objects/Repl.py
rename : python/m5/objects/Root.mpy => python/m5/objects/Root.py
rename : python/m5/objects/SimConsole.mpy => python/m5/objects/SimConsole.py
rename : python/m5/objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.py
rename : python/m5/objects/Tsunami.mpy => python/m5/objects/Tsunami.py
rename : python/m5/objects/Uart.mpy => python/m5/objects/Uart.py
extra : convert_revision : 9dc55103a6f5b40eada4ed181a71a96fae6b0b76
80 lines
3.6 KiB
Python
80 lines
3.6 KiB
Python
from m5 import *
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from BaseCPU import BaseCPU
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class DerivAlphaFullCPU(BaseCPU):
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type = 'DerivAlphaFullCPU'
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numThreads = Param.Unsigned("number of HW thread contexts")
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if not build_env['FULL_SYSTEM']:
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mem = Param.FunctionalMemory(NULL, "memory")
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decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
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renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
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iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
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"delay")
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commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
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fetchWidth = Param.Unsigned("Fetch width")
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renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
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iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
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"delay")
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commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
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fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
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decodeWidth = Param.Unsigned("Decode width")
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iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
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"delay")
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commitToRenameDelay = Param.Unsigned("Commit to rename delay")
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decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
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renameWidth = Param.Unsigned("Rename width")
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commitToIEWDelay = Param.Unsigned("Commit to "
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"Issue/Execute/Writeback delay")
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renameToIEWDelay = Param.Unsigned("Rename to "
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"Issue/Execute/Writeback delay")
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issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
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"to the IEW stage)")
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issueWidth = Param.Unsigned("Issue width")
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executeWidth = Param.Unsigned("Execute width")
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executeIntWidth = Param.Unsigned("Integer execute width")
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executeFloatWidth = Param.Unsigned("Floating point execute width")
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executeBranchWidth = Param.Unsigned("Branch execute width")
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executeMemoryWidth = Param.Unsigned("Memory execute width")
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iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
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"delay")
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renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
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commitWidth = Param.Unsigned("Commit width")
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squashWidth = Param.Unsigned("Squash width")
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local_predictor_size = Param.Unsigned("Size of local predictor")
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local_ctr_bits = Param.Unsigned("Bits per counter")
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local_history_table_size = Param.Unsigned("Size of local history table")
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local_history_bits = Param.Unsigned("Bits for the local history")
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global_predictor_size = Param.Unsigned("Size of global predictor")
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global_ctr_bits = Param.Unsigned("Bits per counter")
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global_history_bits = Param.Unsigned("Bits of history")
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choice_predictor_size = Param.Unsigned("Size of choice predictor")
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choice_ctr_bits = Param.Unsigned("Bits of choice counters")
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BTBEntries = Param.Unsigned("Number of BTB entries")
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BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
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RASSize = Param.Unsigned("RAS size")
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LQEntries = Param.Unsigned("Number of load queue entries")
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SQEntries = Param.Unsigned("Number of store queue entries")
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LFSTSize = Param.Unsigned("Last fetched store table size")
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SSITSize = Param.Unsigned("Store set ID table size")
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numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
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numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
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"registers")
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numIQEntries = Param.Unsigned("Number of instruction queue entries")
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numROBEntries = Param.Unsigned("Number of reorder buffer entries")
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instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
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function_trace = Param.Bool(False, "Enable function trace")
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function_trace_start = Param.Tick(0, "Cycle to start function trace")
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