5c3f724174
Remove this hack once the caches eventually get fixed. --HG-- extra : convert_revision : 8c61ac1b6182f57ebbe3bcfeddb5a4f4334d7bc0
124 lines
5.9 KiB
Python
124 lines
5.9 KiB
Python
from m5.params import *
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from m5.proxy import *
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from m5 import build_env
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from BaseCPU import BaseCPU
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from Checker import O3Checker
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from FUPool import *
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class DerivO3CPU(BaseCPU):
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type = 'DerivO3CPU'
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activity = Param.Unsigned(0, "Initial count")
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numThreads = Param.Unsigned(1, "number of HW thread contexts")
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if build_env['FULL_SYSTEM']:
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profile = Param.Latency('0ns', "trace the kernel stack")
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if build_env['USE_CHECKER']:
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if not build_env['FULL_SYSTEM']:
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checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
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exitOnError=False,
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updateOnError=True,
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warnOnlyOnLoadError=False),
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"checker")
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else:
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checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True,
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warnOnlyOnLoadError=False), "checker")
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checker.itb = Parent.itb
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checker.dtb = Parent.dtb
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cachePorts = Param.Unsigned("Cache Ports")
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icache_port = Port("Instruction Port")
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dcache_port = Port("Data Port")
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_mem_ports = ['icache_port', 'dcache_port']
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decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
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renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")
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iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch "
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"delay")
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commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay")
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fetchWidth = Param.Unsigned(8, "Fetch width")
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renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay")
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iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode "
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"delay")
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commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay")
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fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay")
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decodeWidth = Param.Unsigned(8, "Decode width")
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iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename "
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"delay")
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commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay")
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decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay")
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renameWidth = Param.Unsigned(8, "Rename width")
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commitToIEWDelay = Param.Unsigned(1, "Commit to "
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"Issue/Execute/Writeback delay")
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renameToIEWDelay = Param.Unsigned(2, "Rename to "
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"Issue/Execute/Writeback delay")
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issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal "
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"to the IEW stage)")
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dispatchWidth = Param.Unsigned(8, "Dispatch width")
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issueWidth = Param.Unsigned(8, "Issue width")
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wbWidth = Param.Unsigned(8, "Writeback width")
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wbDepth = Param.Unsigned(1, "Writeback depth")
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fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
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iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit "
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"delay")
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renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay")
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commitWidth = Param.Unsigned(8, "Commit width")
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squashWidth = Param.Unsigned(8, "Squash width")
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trapLatency = Param.Tick(13, "Trap latency")
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fetchTrapLatency = Param.Tick(1, "Fetch trap latency")
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backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
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forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
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predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')")
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localPredictorSize = Param.Unsigned(2048, "Size of local predictor")
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localCtrBits = Param.Unsigned(2, "Bits per counter")
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localHistoryTableSize = Param.Unsigned(2048, "Size of local history table")
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localHistoryBits = Param.Unsigned(11, "Bits for the local history")
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globalPredictorSize = Param.Unsigned(8192, "Size of global predictor")
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globalCtrBits = Param.Unsigned(2, "Bits per counter")
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globalHistoryBits = Param.Unsigned(13, "Bits of history")
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choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor")
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choiceCtrBits = Param.Unsigned(2, "Bits of choice counters")
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BTBEntries = Param.Unsigned(4096, "Number of BTB entries")
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BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits")
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RASSize = Param.Unsigned(16, "RAS size")
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LQEntries = Param.Unsigned(32, "Number of load queue entries")
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SQEntries = Param.Unsigned(32, "Number of store queue entries")
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LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
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SSITSize = Param.Unsigned(1024, "Store set ID table size")
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numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
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numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
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numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
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"registers")
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numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
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numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
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instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by")
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function_trace = Param.Bool(False, "Enable function trace")
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function_trace_start = Param.Tick(0, "Cycle to start function trace")
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smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads")
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smtFetchPolicy = Param.String("SMT Fetch policy")
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smtLSQPolicy = Param.String("SMT LSQ Sharing Policy")
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smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter")
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smtIQPolicy = Param.String("SMT IQ Sharing Policy")
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smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter")
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smtROBPolicy = Param.String("SMT ROB Sharing Policy")
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smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter")
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smtCommitPolicy = Param.String("SMT Commit Policy")
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def addPrivateSplitL1Caches(self, ic, dc):
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BaseCPU.addPrivateSplitL1Caches(self, ic, dc)
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self.icache.tgts_per_mshr = 20
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self.dcache.tgts_per_mshr = 20
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