into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem configs/boot/micro_memlat.rcS: configs/boot/micro_tlblat.rcS: src/arch/alpha/ev5.cc: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa_traits.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.hh: src/cpu/checker/cpu_impl.hh: src/cpu/o3/alpha/cpu_impl.hh: src/cpu/o3/alpha/params.hh: src/cpu/o3/checker_builder.cc: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/lsq_unit_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/checker_builder.cc: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/base.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.hh: src/dev/ide_disk.cc: src/python/m5/objects/O3CPU.py: src/python/m5/objects/Root.py: src/python/m5/objects/System.py: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/system.hh: util/m5/m5.c: Hand merge. --HG-- rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc rename : arch/alpha/system.cc => src/arch/alpha/system.cc rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc rename : cpu/base.cc => src/cpu/base.cc rename : cpu/base.hh => src/cpu/base.hh rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc rename : cpu/thread_state.hh => src/cpu/thread_state.hh rename : dev/ide_disk.hh => src/dev/ide_disk.hh rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py rename : python/m5/objects/System.py => src/python/m5/objects/System.py rename : sim/eventq.hh => src/sim/eventq.hh rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh rename : sim/serialize.cc => src/sim/serialize.cc rename : sim/stat_control.cc => src/sim/stat_control.cc rename : sim/stat_control.hh => src/sim/stat_control.hh rename : sim/system.hh => src/sim/system.hh extra : convert_revision : 135d90e43f6cea89f9460ba4e23f4b0b85886e7d
249 lines
6.1 KiB
C++
249 lines
6.1 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Lisa Hsu
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* Nathan Binkert
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*/
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#ifndef __SYSTEM_HH__
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#define __SYSTEM_HH__
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#include <string>
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#include <vector>
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#include "base/loader/symtab.hh"
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#include "base/misc.hh"
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#include "base/statistics.hh"
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#include "config/full_system.hh"
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#include "cpu/pc_event.hh"
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#include "mem/port.hh"
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#include "sim/sim_object.hh"
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#if FULL_SYSTEM
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#include "kern/system_events.hh"
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#include "mem/vport.hh"
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#endif
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class BaseCPU;
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class ThreadContext;
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class ObjectFile;
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class PhysicalMemory;
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#if FULL_SYSTEM
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class Platform;
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class GDBListener;
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class RemoteGDB;
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#endif
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class System : public SimObject
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{
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public:
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enum MemoryMode {
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Invalid=0,
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Atomic,
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Timing
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};
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static const char *MemoryModeStrings[3];
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MemoryMode getMemoryMode() { assert(memoryMode); return memoryMode; }
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/** Change the memory mode of the system. This should only be called by the
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* python!!
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* @param mode Mode to change to (atomic/timing)
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*/
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void setMemoryMode(MemoryMode mode);
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PhysicalMemory *physmem;
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PCEventQueue pcEventQueue;
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std::vector<ThreadContext *> threadContexts;
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int numcpus;
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int getNumCPUs()
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{
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if (numcpus != threadContexts.size())
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panic("cpu array not fully populated!");
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return numcpus;
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}
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#if FULL_SYSTEM
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Platform *platform;
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uint64_t init_param;
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/** Port to physical memory used for writing object files into ram at
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* boot.*/
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FunctionalPort functionalPort;
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VirtualPort virtPort;
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/** kernel symbol table */
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SymbolTable *kernelSymtab;
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/** Object pointer for the kernel code */
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ObjectFile *kernel;
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/** Begining of kernel code */
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Addr kernelStart;
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/** End of kernel code */
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Addr kernelEnd;
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/** Entry point in the kernel to start at */
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Addr kernelEntry;
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#else
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int page_ptr;
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#endif // FULL_SYSTEM
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protected:
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MemoryMode memoryMode;
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#if FULL_SYSTEM
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/**
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* Fix up an address used to match PCs for hooking simulator
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* events on to target function executions. See comment in
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* system.cc for details.
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*/
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virtual Addr fixFuncEventAddr(Addr addr) = 0;
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/**
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* Add a function-based event to the given function, to be looked
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* up in the specified symbol table.
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*/
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template <class T>
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T *addFuncEvent(SymbolTable *symtab, const char *lbl)
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{
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Addr addr = 0; // initialize only to avoid compiler warning
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if (symtab->findAddress(lbl, addr)) {
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T *ev = new T(&pcEventQueue, lbl, fixFuncEventAddr(addr));
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return ev;
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}
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return NULL;
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}
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/** Add a function-based event to kernel code. */
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template <class T>
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T *addKernelFuncEvent(const char *lbl)
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{
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return addFuncEvent<T>(kernelSymtab, lbl);
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}
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#endif
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public:
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#if FULL_SYSTEM
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std::vector<RemoteGDB *> remoteGDB;
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std::vector<GDBListener *> gdbListen;
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virtual bool breakpoint() = 0;
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#endif // FULL_SYSTEM
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public:
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struct Params
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{
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std::string name;
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PhysicalMemory *physmem;
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MemoryMode mem_mode;
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#if FULL_SYSTEM
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Tick boot_cpu_frequency;
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std::string boot_osflags;
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uint64_t init_param;
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std::string kernel_path;
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std::string readfile;
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std::string symbolfile;
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#endif
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};
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protected:
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Params *_params;
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public:
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System(Params *p);
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~System();
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void startup();
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const Params *params() const { return (const Params *)_params; }
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public:
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#if FULL_SYSTEM
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/**
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* Returns the addess the kernel starts at.
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* @return address the kernel starts at
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*/
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Addr getKernelStart() const { return kernelStart; }
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/**
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* Returns the addess the kernel ends at.
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* @return address the kernel ends at
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*/
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Addr getKernelEnd() const { return kernelEnd; }
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/**
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* Returns the addess the entry point to the kernel code.
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* @return entry point of the kernel code
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*/
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Addr getKernelEntry() const { return kernelEntry; }
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#else
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Addr new_page();
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#endif // FULL_SYSTEM
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int registerThreadContext(ThreadContext *tc, int tcIndex);
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void replaceThreadContext(ThreadContext *tc, int tcIndex);
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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public:
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////////////////////////////////////////////
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//
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// STATIC GLOBAL SYSTEM LIST
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//
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////////////////////////////////////////////
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static std::vector<System *> systemList;
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static int numSystemsRunning;
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static void printSystems();
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};
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#endif // __SYSTEM_HH__
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