gem5/src/sim
Akash Bagdia 7d7ab73862 sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.

The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).

The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.

All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.

The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
2013-06-27 05:49:49 -04:00
..
arguments.cc GetArgument: Rework getArgument so that X86_FS compiles again. 2010-10-15 23:57:06 -07:00
arguments.hh scons: Fix up numerous warnings about name shadowing 2013-02-19 05:56:06 -05:00
async.cc Factor code out of main.cc and main.i into a bunch of files 2007-03-02 22:24:00 -08:00
async.hh style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
BaseTLB.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
byteswap.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
clock_domain.cc sim: Add the notion of clock domains to all ClockedObjects 2013-06-27 05:49:49 -04:00
clock_domain.hh sim: Add the notion of clock domains to all ClockedObjects 2013-06-27 05:49:49 -04:00
ClockDomain.py sim: Add the notion of clock domains to all ClockedObjects 2013-06-27 05:49:49 -04:00
clocked_object.hh sim: Add the notion of clock domains to all ClockedObjects 2013-06-27 05:49:49 -04:00
ClockedObject.py sim: Add the notion of clock domains to all ClockedObjects 2013-06-27 05:49:49 -04:00
core.cc sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
core.hh sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
debug.cc sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
debug.hh scons: Add warning for missing declarations 2013-02-19 05:56:07 -05:00
drain.cc sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
drain.hh scons: Add warning for missing declarations 2013-02-19 05:56:07 -05:00
eventq.cc sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
eventq.hh scons: Add warning for missing declarations 2013-02-19 05:56:07 -05:00
eventq_impl.hh sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
fault_fwd.hh copyright: clean up copyright blocks 2011-06-02 14:36:35 -07:00
faults.cc SE/FS: Get rid of FULL_SYSTEM in sim. 2011-11-02 02:11:14 -07:00
faults.hh SE/FS: Get rid of includes of config/full_system.hh. 2011-11-18 02:20:22 -08:00
full_system.hh clang: Fix recently introduced clang compilation errors 2012-03-19 06:35:04 -04:00
init.cc base: Add wrapped protobuf output streams 2013-01-07 13:05:37 -05:00
init.hh scons: Add warning for missing declarations 2013-02-19 05:56:07 -05:00
insttracer.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
InstTracer.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
main.cc libm5: Create a libm5 static library for embedding m5. 2008-08-03 18:19:54 -07:00
microcode_rom.hh CPU: Create a microcode ROM object in the CPU which is defined by the ISA. 2008-10-12 15:59:21 -07:00
process.cc base: load weak symbols from object file 2013-04-17 16:07:19 -05:00
process.hh process: add progName() virtual function 2012-08-06 16:55:34 -07:00
Process.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
process_impl.hh MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00
pseudo_inst.cc sim: Add debug output when executing pseudo-instructions 2013-06-03 13:21:21 +02:00
pseudo_inst.hh sim: Add a helper function to execute pseudo instructions 2013-04-22 13:20:32 -04:00
root.cc sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
root.hh sim: Provide a framework for detecting out of data checkpoints and migrating them. 2012-06-05 01:23:10 -04:00
Root.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
SConscript sim: Add the notion of clock domains to all ClockedObjects 2013-06-27 05:49:49 -04:00
serialize.cc sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
serialize.hh scons: Add warning for missing declarations 2013-02-19 05:56:07 -05:00
sim_events.cc sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
sim_events.hh sim: clean up CountedDrainEvent slightly. 2011-01-07 21:50:29 -08:00
sim_exit.hh Replace curTick global variable with accessor functions. 2011-01-07 21:50:29 -08:00
sim_object.cc sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
sim_object.hh scons: Add warning for missing declarations 2013-02-19 05:56:07 -05:00
simulate.cc sim: Revert [34e3295b0e39] (sim: Fix early termination in mult...) 2013-06-11 09:24:10 +02:00
simulate.hh types: Move stuff for global types into src/base/types.hh 2009-05-17 14:34:50 -07:00
stat_control.cc stats: Fix swig wrapping for Tick in stats 2013-01-07 16:56:36 -05:00
stat_control.hh scons: Add warning for missing declarations 2013-02-19 05:56:07 -05:00
stats.hh stats: make simTicks and simFreq accessible from stats.hh 2010-04-18 13:23:25 -07:00
syscall_emul.cc arm: add access syscall for ARM SE mode 2013-01-08 08:54:07 -05:00
syscall_emul.hh arm: add access syscall for ARM SE mode 2013-01-08 08:54:07 -05:00
syscallreturn.hh includes: use base/types.hh not inttypes.h or stdint.h 2009-05-17 14:34:51 -07:00
system.cc sim: Add a system-global option to bypass caches 2013-02-15 17:40:09 -05:00
system.hh sim: Add helper functions that add PCEvents with custom arguments 2013-04-22 13:20:31 -04:00
System.py config: Add a system clock command-line option 2013-06-27 05:49:49 -04:00
tlb.cc arch: Create a method to finalize physical addresses 2013-06-03 13:55:41 +02:00
tlb.hh arch: Create a method to finalize physical addresses 2013-06-03 13:55:41 +02:00
vptr.hh MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00