f9d403a7b9
This patch introduces the notion of a master and slave port in the C++ code, thus bringing the previous classification from the Python classes into the corresponding simulation objects and memory objects. The patch enables us to classify behaviours into the two bins and add assumptions and enfore compliance, also simplifying the two interfaces. As a starting point, isSnooping is confined to a master port, and getAddrRanges to slave ports. More of these specilisations are to come in later patches. The getPort function is not getMasterPort and getSlavePort, and returns a port reference rather than a pointer as NULL would never be a valid return value. The default implementation of these two functions is placed in MemObject, and calls fatal. The one drawback with this specific patch is that it requires some code duplication, e.g. QueuedPort becomes QueuedMasterPort and QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort (avoiding multiple inheritance). With the later introduction of the port interfaces, moving the functionality outside the port itself, a lot of the duplicated code will disappear again.
104 lines
4.3 KiB
C++
104 lines
4.3 KiB
C++
/*
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* Copyright (c) 2011 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Andreas Hansson
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*/
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/**
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* @file
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* TranslatingPortProxy Object Declaration for FS.
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*
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* Port proxies are used when non structural entities need access to
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* the memory system. Proxy objects replace the previous
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* FunctionalPort, TranslatingPort and VirtualPort objects, which
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* provided the same functionality as the proxies, but were instances
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* of ports not corresponding to real structural ports of the
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* simulated system. Via the port proxies all the accesses go through
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* an actual port and thus are transparent to a potentially
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* distributed memory and automatically adhere to the memory map of
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* the system.
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*/
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#ifndef __MEM_FS_PORT_PROXY_HH__
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#define __MEM_FS_PORT_PROXY_HH__
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#include "arch/vtophys.hh"
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#include "mem/port_proxy.hh"
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/**
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* A TranslatingPortProxy in FS mode translates a virtual address to a
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* physical address and then calls the read/write functions of the
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* port. If a thread context is provided the address can alway be
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* translated, If not it can only be translated if it is a simple
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* address masking operation (such as alpha super page accesses).
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*/
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class FSTranslatingPortProxy : public PortProxy
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{
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private:
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ThreadContext* _tc;
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public:
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FSTranslatingPortProxy(ThreadContext* tc);
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FSTranslatingPortProxy(MasterPort &port);
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virtual ~FSTranslatingPortProxy();
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/** Version of readblob that translates virt->phys and deals
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* with page boundries. */
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virtual void readBlob(Addr addr, uint8_t *p, int size) const;
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/** Version of writeBlob that translates virt->phys and deals
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* with page boundries. */
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virtual void writeBlob(Addr addr, uint8_t *p, int size) const;
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/**
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* Fill size bytes starting at addr with byte value val.
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*/
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virtual void memsetBlob(Addr address, uint8_t v, int size) const;
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};
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void CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen);
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void CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen);
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void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen);
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void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr);
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#endif //__MEM_FS_PORT_PROXY_HH__
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