baba18ab92
First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model.
Second: Include build options for selecting the Checker to be used. These options make sure if the Checker is being used there is a CPU that supports it also being compiled.
SConstruct:
Add in option USE_CHECKER to allow for not compiling in checker code. The checker is enabled through this option instead of through the CPU_MODELS list. However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled.
configs/test/test.py:
Name change for DetailedCPU to DetailedO3CPU. Also include option for max tick.
src/base/traceflags.py:
Add in O3CPU trace flag.
src/cpu/SConscript:
Rename AlphaFullCPU to AlphaO3CPU.
Only include checker sources if they're necessary. Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included.
src/cpu/base_dyn_inst.cc:
src/cpu/base_dyn_inst.hh:
Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU.
src/cpu/cpu_models.py:
src/cpu/o3/alpha_cpu.cc:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_cpu_impl.hh:
Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model.
src/cpu/o3/alpha_dyn_inst.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/alpha_impl.hh:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
src/cpu/o3/thread_state.hh:
src/python/m5/objects/AlphaO3CPU.py:
Rename FullCPU to O3CPU to differentiate from old FullCPU model.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
Rename FullCPU to O3CPU to differentiate from old FullCPU model.
Also #ifdef the checker code so it doesn't need to be included if it's not selected.
--HG--
rename : src/cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_builder.cc
rename : src/cpu/checker/cpu_builder.cc => src/cpu/checker/ozone_builder.cc
rename : src/python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaO3CPU.py
extra : convert_revision : 86619baf257b8b7c8955efd447eba56e0d7acd6a
82 lines
3.5 KiB
Python
82 lines
3.5 KiB
Python
# Copyright (c) 2003-2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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################
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# CpuModel class
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#
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# The CpuModel class encapsulates everything the ISA parser needs to
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# know about a particular CPU model.
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class CpuModel:
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# Dict of available CPU model objects. Accessible as CpuModel.dict.
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dict = {}
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# Constructor. Automatically adds models to CpuModel.dict.
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def __init__(self, name, filename, includes, strings):
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self.name = name
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self.filename = filename # filename for output exec code
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self.includes = includes # include files needed in exec file
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# The 'strings' dict holds all the per-CPU symbols we can
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# substitute into templates etc.
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self.strings = strings
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# Add self to dict
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CpuModel.dict[name] = self
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#
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# Define CPU models.
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#
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# Parameters are:
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# - name of model
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# - filename for generated ISA execution file
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# - includes needed for generated ISA execution file
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# - substitution strings for ISA description templates
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#
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CpuModel('AtomicSimpleCPU', 'atomic_simple_cpu_exec.cc',
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'#include "cpu/simple/atomic.hh"',
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{ 'CPU_exec_context': 'AtomicSimpleCPU' })
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CpuModel('TimingSimpleCPU', 'timing_simple_cpu_exec.cc',
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'#include "cpu/simple/timing.hh"',
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{ 'CPU_exec_context': 'TimingSimpleCPU' })
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CpuModel('FullCPU', 'full_cpu_exec.cc',
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'#include "encumbered/cpu/full/dyn_inst.hh"',
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{ 'CPU_exec_context': 'DynInst' })
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CpuModel('AlphaO3CPU', 'alpha_o3_exec.cc',
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'#include "cpu/o3/alpha_dyn_inst.hh"',
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{ 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' })
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CpuModel('OzoneSimpleCPU', 'ozone_simple_exec.cc',
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'#include "cpu/ozone/dyn_inst.hh"',
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{ 'CPU_exec_context': 'OzoneDynInst<SimpleImpl>' })
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CpuModel('OzoneCPU', 'ozone_exec.cc',
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'#include "cpu/ozone/dyn_inst.hh"',
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{ 'CPU_exec_context': 'OzoneDynInst<OzoneImpl>' })
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CpuModel('CheckerCPU', 'checker_cpu_exec.cc',
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'#include "cpu/checker/cpu.hh"',
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{ 'CPU_exec_context': 'CheckerCPU' })
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