Nilay Vaish 4d4d212ae9 X86: Split Condition Code register ... This patch moves the ECF and EZF bits to individual registers (ecfBit and ezfBit) and the CF and OF bits to cfofFlag registers. This is being done so as to lower the read after write dependencies on the the condition code register. Ultimately we will have the following registers [ZAPS], [OF], [CF], [ECF], [EZF] and [DF]. Note that this is only one part of the solution for lowering the dependencies. The other part will check whether or not the condition code register needs to be actually read. This would be done through a separate patch.		2012-05-22 11:29:53 -05:00
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base.isa	GCC: Get everything working with gcc 4.6.1.	2011-10-31 01:09:44 -07:00
debug.isa	X86: Split Condition Code register	2012-05-22 11:29:53 -05:00
fpop.isa	X86: Split Condition Code register	2012-05-22 11:29:53 -05:00
ldstop.isa	X86: Fix address size handling so real mode works properly.	2012-03-31 12:27:33 -07:00
limmop.isa	ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.	2011-09-26 23:48:54 -07:00
mediaop.isa	X86: Split Condition Code register	2012-05-22 11:29:53 -05:00
microops.isa	copyright: Change HP copyright on x86 code to be more friendly	2010-05-23 22:44:15 -07:00
regop.isa	X86: Split Condition Code register	2012-05-22 11:29:53 -05:00
seqop.isa	X86: Split Condition Code register	2012-05-22 11:29:53 -05:00
specop.isa	X86: Split Condition Code register	2012-05-22 11:29:53 -05:00