e65de3f5ca
This patch generalises the address range resolution for the I/O cache and I/O bridge such that they do not assume a single memory. The patch involves adding a parameter to the system which is then defined based on the memories that are to be visible from the I/O subsystem, whether behind a cache or a bridge. The change is needed to allow interleaved memory controllers in the system. |
||
---|---|---|
.. | ||
boot | ||
common | ||
example | ||
ruby | ||
splash2 | ||
topologies |