Gabe Black 4bdabe1254 Add a flag to indicate an instruction triggers a syscall in SE mode. ... --HG-- extra : convert_revision : 1d0b3afdd8254f5b2fb4bbff1fa4a0536f78bb06		2007-07-31 17:34:08 -07:00
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formats	Merge zizzer.eecs.umich.edu:/bk/newmem	2007-06-19 18:54:40 -07:00
base.isa	Create a filter and a union to translate the SPARC instruction implementations from using doubles to using concatenated singles.	2007-04-11 12:25:00 +00:00
bitfields.isa	add pseduo instruction support for sparc	2007-02-21 21:06:17 -05:00
decoder.isa	Add a flag to indicate an instruction triggers a syscall in SE mode.	2007-07-31 17:34:08 -07:00
includes.isa	create base/fenv.c to standerdize fenv across platforms. It's a c file and not a cpp file because c99	2007-04-21 17:50:47 -04:00
main.isa	Broke Load/Store instructions into microcode, and partially refactored memory operations in the SPARC ISA description.	2006-10-23 07:55:52 -04:00
operands.isa	Make the GSR into a renamed control register. It should be split into a renamed part and a control part for the different bitfields, but the renamed part is all that's actually used.	2007-04-22 17:43:45 +00:00