864 lines
99 KiB
Plaintext
864 lines
99 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.119236 # Number of seconds simulated
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sim_ticks 1119236001500 # Number of ticks simulated
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final_tick 1119236001500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 240571 # Simulator instruction rate (inst/s)
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host_op_rate 259178 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 174324523 # Simulator tick rate (ticks/s)
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host_mem_usage 314620 # Number of bytes of host memory used
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host_seconds 6420.42 # Real time elapsed on the host
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sim_insts 1544563088 # Number of instructions simulated
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sim_ops 1664032481 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 50432 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 131457472 # Number of bytes read from this memory
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system.physmem.bytes_read::total 131507904 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 50432 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 50432 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 66959680 # Number of bytes written to this memory
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system.physmem.bytes_written::total 66959680 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 788 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 2054023 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 2054811 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1046245 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1046245 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 45059 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 117452862 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 117497922 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 45059 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 45059 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 59826239 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 59826239 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 59826239 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 45059 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 117452862 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 177324160 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 2054811 # Number of read requests accepted
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system.physmem.writeReqs 1046245 # Number of write requests accepted
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system.physmem.readBursts 2054811 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 1046245 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 131422592 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 85312 # Total number of bytes read from write queue
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system.physmem.bytesWritten 66958080 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 131507904 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 66959680 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 1333 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 127863 # Per bank write bursts
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system.physmem.perBankRdBursts::1 125217 # Per bank write bursts
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system.physmem.perBankRdBursts::2 122173 # Per bank write bursts
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system.physmem.perBankRdBursts::3 124176 # Per bank write bursts
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system.physmem.perBankRdBursts::4 123271 # Per bank write bursts
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system.physmem.perBankRdBursts::5 123280 # Per bank write bursts
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system.physmem.perBankRdBursts::6 123668 # Per bank write bursts
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system.physmem.perBankRdBursts::7 124134 # Per bank write bursts
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system.physmem.perBankRdBursts::8 131770 # Per bank write bursts
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system.physmem.perBankRdBursts::9 134069 # Per bank write bursts
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system.physmem.perBankRdBursts::10 132400 # Per bank write bursts
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system.physmem.perBankRdBursts::11 133571 # Per bank write bursts
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system.physmem.perBankRdBursts::12 133882 # Per bank write bursts
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system.physmem.perBankRdBursts::13 133894 # Per bank write bursts
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system.physmem.perBankRdBursts::14 129882 # Per bank write bursts
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system.physmem.perBankRdBursts::15 130228 # Per bank write bursts
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system.physmem.perBankWrBursts::0 65769 # Per bank write bursts
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system.physmem.perBankWrBursts::1 64155 # Per bank write bursts
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system.physmem.perBankWrBursts::2 62373 # Per bank write bursts
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system.physmem.perBankWrBursts::3 62858 # Per bank write bursts
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system.physmem.perBankWrBursts::4 62829 # Per bank write bursts
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system.physmem.perBankWrBursts::5 62965 # Per bank write bursts
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system.physmem.perBankWrBursts::6 64230 # Per bank write bursts
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system.physmem.perBankWrBursts::7 65234 # Per bank write bursts
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system.physmem.perBankWrBursts::8 67002 # Per bank write bursts
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system.physmem.perBankWrBursts::9 67576 # Per bank write bursts
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system.physmem.perBankWrBursts::10 67286 # Per bank write bursts
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system.physmem.perBankWrBursts::11 67640 # Per bank write bursts
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system.physmem.perBankWrBursts::12 67022 # Per bank write bursts
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system.physmem.perBankWrBursts::13 67467 # Per bank write bursts
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system.physmem.perBankWrBursts::14 66208 # Per bank write bursts
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system.physmem.perBankWrBursts::15 65606 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 1119235907000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 2054811 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 1046245 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 1925781 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 127679 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 32244 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 33494 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 56963 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 61003 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 61383 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 61457 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 61389 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 61438 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 61514 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 61512 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 61526 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 61507 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 62283 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 61797 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 61801 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 62618 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 61214 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 60967 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1918760 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 103.389572 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 81.724365 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 124.748032 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 1494097 77.87% 77.87% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 305195 15.91% 93.77% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 52958 2.76% 96.53% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 21140 1.10% 97.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 13031 0.68% 98.31% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 7420 0.39% 98.70% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 5500 0.29% 98.99% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 5087 0.27% 99.25% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 14332 0.75% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1918760 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 60963 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 33.636353 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 160.963797 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 60925 99.94% 99.94% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 12 0.02% 99.96% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 60963 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 60963 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 17.161557 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 17.126473 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 1.099462 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 27343 44.85% 44.85% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::17 1128 1.85% 46.70% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 28298 46.42% 93.12% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 3779 6.20% 99.32% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20 354 0.58% 99.90% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::21 49 0.08% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::22 6 0.01% 99.99% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::23 2 0.00% 99.99% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 60963 # Writes before turning the bus around for reads
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system.physmem.totQLat 38392697500 # Total ticks spent queuing
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system.physmem.totMemAccLat 76895410000 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 10267390000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 18696.43 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 37446.43 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 117.42 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 59.82 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 117.50 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 59.83 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 1.38 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 25.22 # Average write queue length when enqueuing
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system.physmem.readRowHits 774740 # Number of row buffer hits during reads
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system.physmem.writeRowHits 406194 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 37.73 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 38.82 # Row buffer hit rate for writes
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system.physmem.avgGap 360920.90 # Average gap between requests
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system.physmem.pageHitRate 38.10 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 7079751000 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 3862959375 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 7751413800 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 3307476240 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 73102957200 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 422173404720 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 301213311750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 818491274085 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 731.295434 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 498371051250 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 37373700000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 583490028750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 7426074600 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 4051925625 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 8265605400 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 3472029360 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 73102957200 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 430406880300 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 293990964750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 820716437235 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 733.283545 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 486308465000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 37373700000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 595553667000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 239764270 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 186476421 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 14595676 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 130796554 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 122091083 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 93.344266 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 15654091 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 46 # Number of system calls
|
|
system.cpu.numCycles 2238472003 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 1544563088 # Number of instructions committed
|
|
system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 41626992 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
|
system.cpu.cpi 1.449259 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.690008 # IPC: instructions per cycle
|
|
system.cpu.tickCycles 1834950604 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 403521399 # Total number of cycles that the object has spent stopped
|
|
system.cpu.dcache.tags.replacements 9221835 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4085.627405 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 624240644 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 9225931 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 67.661534 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 9809256250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4085.627405 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.997468 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.997468 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 244 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1227 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2564 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 1276887063 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 1276887063 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 453909121 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 453909121 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 170331400 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 170331400 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 624240521 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 624240521 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 624240522 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 624240522 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 7335273 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 7335273 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 2254647 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 2254647 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 9589920 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 9589920 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 9589922 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 9589922 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 192354012246 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 192354012246 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 109627439500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 109627439500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 301981451746 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 301981451746 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 301981451746 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 301981451746 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 461244394 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 461244394 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 633830441 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 633830441 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 633830444 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 633830444 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015903 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.015903 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013064 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.013064 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26223.156554 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 26223.156554 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48622.883981 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 48622.883981 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31489.465162 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 31489.465162 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31489.458595 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 31489.458595 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 3700642 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 3700642 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 363775 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 363775 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 363990 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 363990 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 363990 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 363990 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7335058 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 7335058 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890872 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1890872 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 9225930 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 9225930 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 9225931 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 9225931 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180934230004 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 180934230004 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83925664500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 83925664500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 73750 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 73750 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264859894504 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 264859894504 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264859968254 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 264859968254 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015903 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015903 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014556 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.014556 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014556 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.014556 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24667.048305 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24667.048305 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44384.635502 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44384.635502 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 73750 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 73750 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28708.205515 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28708.205515 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28708.210397 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28708.210397 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 29 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 662.446494 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 465464024 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 821 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 566947.654080 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 662.446494 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.323460 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.323460 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 792 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 755 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.386719 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 930930511 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 930930511 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 465464024 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 465464024 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 465464024 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 465464024 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 465464024 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 465464024 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 821 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 821 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 821 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 821 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 821 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 821 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 63001249 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 63001249 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 63001249 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 63001249 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 63001249 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 63001249 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 465464845 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 465464845 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 465464845 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 465464845 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 465464845 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 465464845 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76737.209501 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 76737.209501 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76737.209501 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 76737.209501 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76737.209501 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 76737.209501 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 821 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 821 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 821 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 821 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 821 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 821 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61437251 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 61437251 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61437251 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 61437251 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61437251 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 61437251 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74832.218027 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74832.218027 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74832.218027 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 74832.218027 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74832.218027 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 74832.218027 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 2022107 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 31260.648625 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 8983908 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 2051882 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 4.378375 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 59777107750 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 14976.284316 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.749735 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 16257.614575 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.457040 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000816 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.496143 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.953999 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1244 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12852 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15557 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 107361906 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 107361906 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 6080985 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 6081017 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 3700642 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 3700642 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 1090919 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 1090919 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 7171904 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 7171936 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 7171904 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 7171936 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 789 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 1254074 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 1254863 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 799953 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 799953 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 789 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 2054027 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 2054816 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 789 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 2054027 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 2054816 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60278250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 109743015750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 109803294000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70520146000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 70520146000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 60278250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 180263161750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 180323440000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 60278250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 180263161750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 180323440000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 821 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 7335059 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 7335880 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 3700642 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 3700642 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890872 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1890872 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 821 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 9225931 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 9226752 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 821 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 9225931 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 9226752 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961023 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.170970 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.171058 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423060 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.423060 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961023 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.222636 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.222702 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961023 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.222636 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.222702 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76398.288973 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87509.202607 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 87502.216577 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88155.361627 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88155.361627 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76398.288973 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87760.853071 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 87756.490119 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76398.288973 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87760.853071 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 87756.490119 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 1046245 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 1046245 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 788 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1254070 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1254858 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 799953 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 799953 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 788 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 2054023 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 2054811 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 788 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 2054023 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 2054811 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 50399250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 93887019000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 93937418250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60414024000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60414024000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50399250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154301043000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 154351442250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50399250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154301043000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 154351442250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959805 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.170969 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171058 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423060 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423060 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959805 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222636 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.222701 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959805 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222636 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.222701 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63958.439086 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74865.851986 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74859.002572 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75521.966916 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75521.966916 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63958.439086 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75121.380335 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75117.099456 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63958.439086 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75121.380335 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75117.099456 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 7335880 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 7335880 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 3700642 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1890872 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1890872 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1642 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22152504 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 22154146 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52544 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827300672 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 827353216 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 12927394 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 12927394 100.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 12927394 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 10164339000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1397749 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 14187903746 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadReq 1254858 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 1254858 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 1046245 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 799953 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 799953 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5155867 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 5155867 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198467584 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 198467584 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 3101056 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 3101056 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 3101056 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 7929911000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 11237799750 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 1.0 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|