1618 lines
191 KiB
Text
1618 lines
191 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 5.122213 # Number of seconds simulated
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sim_ticks 5122212682000 # Number of ticks simulated
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final_tick 5122212682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 178126 # Simulator instruction rate (inst/s)
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host_op_rate 352092 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2236626113 # Simulator tick rate (ticks/s)
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host_mem_usage 810964 # Number of bytes of host memory used
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host_seconds 2290.15 # Real time elapsed on the host
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sim_insts 407934867 # Number of instructions simulated
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sim_ops 806343968 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 1047104 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 10801152 # Number of bytes read from this memory
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system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
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system.physmem.bytes_read::total 11881280 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 1047104 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1047104 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 9569088 # Number of bytes written to this memory
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system.physmem.bytes_written::total 9569088 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.dtb.walker 66 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 16361 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 168768 # Number of read requests responded to by this memory
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system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 185645 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 149517 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 149517 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.dtb.walker 825 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 204424 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 2108689 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::pc.south_bridge.ide 5535 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2319560 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 204424 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 204424 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1868155 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 1868155 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1868155 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 825 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 204424 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 2108689 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::pc.south_bridge.ide 5535 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 4187715 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 185645 # Number of read requests accepted
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system.physmem.writeReqs 196237 # Number of write requests accepted
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system.physmem.readBursts 185645 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 196237 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 11872960 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue
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system.physmem.bytesWritten 10880320 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 11881280 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 12559168 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 26214 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 1708 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 11253 # Per bank write bursts
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system.physmem.perBankRdBursts::1 10547 # Per bank write bursts
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system.physmem.perBankRdBursts::2 11972 # Per bank write bursts
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system.physmem.perBankRdBursts::3 11655 # Per bank write bursts
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system.physmem.perBankRdBursts::4 11971 # Per bank write bursts
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system.physmem.perBankRdBursts::5 11254 # Per bank write bursts
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system.physmem.perBankRdBursts::6 11364 # Per bank write bursts
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system.physmem.perBankRdBursts::7 11315 # Per bank write bursts
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system.physmem.perBankRdBursts::8 11445 # Per bank write bursts
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system.physmem.perBankRdBursts::9 11672 # Per bank write bursts
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system.physmem.perBankRdBursts::10 11062 # Per bank write bursts
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system.physmem.perBankRdBursts::11 11423 # Per bank write bursts
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system.physmem.perBankRdBursts::12 12308 # Per bank write bursts
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system.physmem.perBankRdBursts::13 12737 # Per bank write bursts
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system.physmem.perBankRdBursts::14 11748 # Per bank write bursts
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system.physmem.perBankRdBursts::15 11789 # Per bank write bursts
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system.physmem.perBankWrBursts::0 11864 # Per bank write bursts
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system.physmem.perBankWrBursts::1 10686 # Per bank write bursts
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system.physmem.perBankWrBursts::2 10651 # Per bank write bursts
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system.physmem.perBankWrBursts::3 9860 # Per bank write bursts
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system.physmem.perBankWrBursts::4 10294 # Per bank write bursts
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system.physmem.perBankWrBursts::5 10368 # Per bank write bursts
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system.physmem.perBankWrBursts::6 9733 # Per bank write bursts
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system.physmem.perBankWrBursts::7 9712 # Per bank write bursts
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system.physmem.perBankWrBursts::8 9632 # Per bank write bursts
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system.physmem.perBankWrBursts::9 10471 # Per bank write bursts
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system.physmem.perBankWrBursts::10 10725 # Per bank write bursts
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system.physmem.perBankWrBursts::11 10392 # Per bank write bursts
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system.physmem.perBankWrBursts::12 11457 # Per bank write bursts
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system.physmem.perBankWrBursts::13 11384 # Per bank write bursts
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system.physmem.perBankWrBursts::14 11667 # Per bank write bursts
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system.physmem.perBankWrBursts::15 11109 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 85 # Number of times write queue was full causing retry
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system.physmem.totGap 5122212630000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 185645 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 196237 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 171240 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 11542 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 1948 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 451 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 1627 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 1832 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 6256 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 6771 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 7099 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 7167 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 7342 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 7542 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 8781 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 7845 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 7971 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 9622 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 8300 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::28 7727 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 10480 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 8737 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 8045 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 7914 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 1477 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 1264 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 1705 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::36 2725 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 2849 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 2539 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::39 2444 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 3285 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::41 2479 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::42 2385 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 2208 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 2459 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 2080 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 1741 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 1599 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 1189 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 975 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 483 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::51 399 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 342 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 363 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::54 239 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 232 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 292 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 197 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 189 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 194 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 152 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 120 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::63 200 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 73901 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 307.887796 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 180.352303 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 329.737558 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 28243 38.22% 38.22% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 17330 23.45% 61.67% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 7468 10.11% 71.77% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::384-511 4217 5.71% 77.48% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::512-639 3016 4.08% 81.56% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::640-767 1973 2.67% 84.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 1390 1.88% 86.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 1267 1.71% 87.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 8997 12.17% 100.00% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::total 73901 # Bytes accessed per row activation
|
|
system.physmem.rdPerTurnAround::samples 6788 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::mean 27.329258 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::stdev 584.024068 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::0-2047 6787 99.99% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 6788 # Reads before turning the bus around for writes
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|
system.physmem.wrPerTurnAround::samples 6788 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::mean 25.044932 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 18.591825 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::stdev 43.260290 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::16-31 6382 94.02% 94.02% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-47 87 1.28% 95.30% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-63 9 0.13% 95.43% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-79 9 0.13% 95.57% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-95 22 0.32% 95.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-111 15 0.22% 96.11% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-127 29 0.43% 96.54% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-143 26 0.38% 96.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-159 35 0.52% 97.44% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-175 9 0.13% 97.57% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-191 41 0.60% 98.17% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::192-207 54 0.80% 98.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::208-223 7 0.10% 99.07% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::224-239 6 0.09% 99.16% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::256-271 1 0.01% 99.18% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::272-287 4 0.06% 99.23% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::288-303 2 0.03% 99.26% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::304-319 4 0.06% 99.32% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::320-335 3 0.04% 99.37% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::336-351 5 0.07% 99.44% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::352-367 19 0.28% 99.72% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::368-383 6 0.09% 99.81% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::384-399 1 0.01% 99.82% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::400-415 1 0.01% 99.84% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::464-479 1 0.01% 99.85% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::480-495 1 0.01% 99.87% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::496-511 3 0.04% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::512-527 1 0.01% 99.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::544-559 1 0.01% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::560-575 4 0.06% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 6788 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 2015945224 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 5494351474 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 927575000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 10866.75 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 29616.75 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 2.12 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.03 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 22.03 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 152167 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 129451 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 82.02 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 13413076.89 # Average gap between requests
|
|
system.physmem.pageHitRate 79.21 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 269256960 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 146916000 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 712374000 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 538928640 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 334557721680 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 129214187775 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 2959979121750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 3425418506805 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 668.738637 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 4924130039468 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 171041780000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 27040752032 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 289434600 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 157925625 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 734635200 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 562703760 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 334557721680 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 129751534755 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 2959507764750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 3425561720370 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 668.766596 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 4923333713433 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 171041780000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 27832687817 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 86818912 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 86818912 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 895085 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 80098723 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 78142837 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 97.558156 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 1551403 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 180089 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
|
system.cpu.numCycles 449999443 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 27536923 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 428761982 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 86818912 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 79694240 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 418469892 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 1877186 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.TlbCycles 142405 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu.fetch.MiscStallCycles 58257 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 203994 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.PendingQuiesceStallCycles 110 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 541 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 9116293 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 453128 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.ItlbSquashes 4723 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 447350715 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 1.891249 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.050769 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 282061925 63.05% 63.05% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 2147503 0.48% 63.53% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 72168287 16.13% 79.66% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 1568006 0.35% 80.01% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 2127596 0.48% 80.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 2318806 0.52% 81.01% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 1512611 0.34% 81.35% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 1884650 0.42% 81.77% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 81561331 18.23% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 447350715 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.192931 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.952806 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 22908567 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 265367852 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 150702709 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 7432994 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 938593 # Number of cycles decode is squashing
|
|
system.cpu.decode.DecodedInsts 837990299 # Number of instructions handled by decode
|
|
system.cpu.rename.SquashCycles 938593 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 25758226 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 223276953 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 12890661 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 154592541 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 29893741 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 834466404 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 451836 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 12178537 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 145180 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 14794285 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 996780528 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 1812316725 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 1114082490 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 470 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 964296204 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 32484322 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 461178 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 464876 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 38644871 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 17242919 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 10123129 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1280249 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 1072002 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 828945592 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 1192163 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 823760090 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 244912 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 23793782 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 35793426 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 146866 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 447350715 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.841419 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 2.417821 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 263279849 58.85% 58.85% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 13891965 3.11% 61.96% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 9851915 2.20% 64.16% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 7048956 1.58% 65.74% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 74303394 16.61% 82.35% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 4391366 0.98% 83.33% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 72807233 16.28% 99.60% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 1204673 0.27% 99.87% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 571364 0.13% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 447350715 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 1986394 72.18% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 608344 22.10% 94.28% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 157420 5.72% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 285236 0.03% 0.03% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 795541833 96.57% 96.61% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 150365 0.02% 96.63% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 127447 0.02% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 108 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.64% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 18320687 2.22% 98.87% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 9334414 1.13% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 823760090 # Type of FU issued
|
|
system.cpu.iq.rate 1.830580 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 2752158 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.003341 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 2097867450 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 853943468 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 819213197 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 514 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 630 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 182 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 826226763 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 249 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 1860072 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 3252614 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 14803 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 14318 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 1702580 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 2208153 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 72229 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 938593 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 204923881 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 10223668 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 830137755 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 158534 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 17242919 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 10123129 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 698460 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 397050 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 8973453 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 14318 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 514177 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 531213 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 1045390 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 822137992 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 17928402 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1491599 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 27038601 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 83256358 # Number of branches executed
|
|
system.cpu.iew.exec_stores 9110199 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.826976 # Inst execution rate
|
|
system.cpu.iew.wb_sent 821634339 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 819213379 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 640695638 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 1049922326 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.820476 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.610231 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 23667492 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 1045297 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 906773 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 443789392 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.816952 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.674122 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 272960111 61.51% 61.51% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 11180384 2.52% 64.03% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 3592831 0.81% 64.84% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 74586039 16.81% 81.64% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 2426818 0.55% 82.19% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 1631046 0.37% 82.56% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 941888 0.21% 82.77% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 71056225 16.01% 98.78% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 5414050 1.22% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 443789392 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 407934867 # Number of instructions committed
|
|
system.cpu.commit.committedOps 806343968 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 22410853 # Number of memory references committed
|
|
system.cpu.commit.loads 13990304 # Number of loads committed
|
|
system.cpu.commit.membars 471837 # Number of memory barriers committed
|
|
system.cpu.commit.branches 82192569 # Number of branches committed
|
|
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 735158454 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 1155650 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 171552 0.02% 0.02% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 783497766 97.17% 97.19% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 144918 0.02% 97.21% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 121442 0.02% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 13987725 1.73% 98.96% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 8420549 1.04% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 806343968 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 5414050 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 1268308634 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 1663603607 # The number of ROB writes
|
|
system.cpu.timesIdled 289860 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 2648728 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.quiesceCycles 9794423343 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu.committedInsts 407934867 # Number of Instructions Simulated
|
|
system.cpu.committedOps 806343968 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 1.103116 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 1.103116 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.906523 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.906523 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 1091825743 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 655727641 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 182 # number of floating regfile reads
|
|
system.cpu.cc_regfile_reads 416065488 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 321934300 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 265346710 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 399949 # number of misc regfile writes
|
|
system.cpu.dcache.tags.replacements 1659310 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.993990 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 19061899 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1659822 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 11.484303 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 41264250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.993990 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 88087332 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 88087332 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 10917280 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 10917280 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 8077307 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 8077307 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 64579 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 64579 # number of SoftPFReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 18994587 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 18994587 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 19059166 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 19059166 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1807757 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1807757 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 333541 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 333541 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 406408 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 406408 # number of SoftPFReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2141298 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2141298 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2547706 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2547706 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 27202744445 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 27202744445 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 13955718277 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 13955718277 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 41158462722 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 41158462722 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 41158462722 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 41158462722 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 12725037 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 12725037 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 8410848 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 8410848 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 470987 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 470987 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 21135885 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 21135885 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 21606872 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 21606872 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142063 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.142063 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039656 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.039656 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.862886 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.862886 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.101311 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.101311 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.117912 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.117912 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15047.788196 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 15047.788196 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41841.087833 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 41841.087833 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19221.267998 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 19221.267998 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16155.106877 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 16155.106877 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 414660 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 43514 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.529347 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 1560749 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 1560749 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 839489 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 839489 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 42702 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 42702 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 882191 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 882191 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 882191 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 882191 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968268 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 968268 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290839 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 290839 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402958 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 402958 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1259107 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1259107 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1662065 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1662065 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 604701 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 604701 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13919 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 13919 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 618620 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 618620 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12834468768 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 12834468768 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12344104823 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12344104823 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5960784250 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5960784250 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25178573591 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 25178573591 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31139357841 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 31139357841 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97454292000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97454292000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2593348000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2593348000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100047640000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 100047640000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076092 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076092 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034579 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034579 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855561 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855561 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059572 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.059572 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076923 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.076923 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13255.078933 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13255.078933 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42443.086460 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42443.086460 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14792.569573 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14792.569573 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19997.167509 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19997.167509 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.342987 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.342987 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161161.122604 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 161161.122604 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 186317.120483 # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186317.120483 # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 161727.134590 # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 161727.134590 # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dtb_walker_cache.tags.replacements 77765 # number of replacements
|
|
system.cpu.dtb_walker_cache.tags.tagsinuse 13.263782 # Cycle average of tags in use
|
|
system.cpu.dtb_walker_cache.tags.total_refs 104942 # Total number of references to valid blocks.
|
|
system.cpu.dtb_walker_cache.tags.sampled_refs 77779 # Sample count of references to valid blocks.
|
|
system.cpu.dtb_walker_cache.tags.avg_refs 1.349233 # Average number of references to valid blocks.
|
|
system.cpu.dtb_walker_cache.tags.warmup_cycle 5097981011500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.263782 # Average occupied blocks per requestor
|
|
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.828986 # Average percentage of cache occupancy
|
|
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.828986 # Average percentage of cache occupancy
|
|
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
|
|
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
|
|
system.cpu.dtb_walker_cache.tags.tag_accesses 446439 # Number of tag accesses
|
|
system.cpu.dtb_walker_cache.tags.data_accesses 446439 # Number of data accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 104946 # number of ReadReq hits
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::total 104946 # number of ReadReq hits
|
|
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 104946 # number of demand (read+write) hits
|
|
system.cpu.dtb_walker_cache.demand_hits::total 104946 # number of demand (read+write) hits
|
|
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 104946 # number of overall hits
|
|
system.cpu.dtb_walker_cache.overall_hits::total 104946 # number of overall hits
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 78849 # number of ReadReq misses
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::total 78849 # number of ReadReq misses
|
|
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 78849 # number of demand (read+write) misses
|
|
system.cpu.dtb_walker_cache.demand_misses::total 78849 # number of demand (read+write) misses
|
|
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 78849 # number of overall misses
|
|
system.cpu.dtb_walker_cache.overall_misses::total 78849 # number of overall misses
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 941548961 # number of ReadReq miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 941548961 # number of ReadReq miss cycles
|
|
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 941548961 # number of demand (read+write) miss cycles
|
|
system.cpu.dtb_walker_cache.demand_miss_latency::total 941548961 # number of demand (read+write) miss cycles
|
|
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 941548961 # number of overall miss cycles
|
|
system.cpu.dtb_walker_cache.overall_miss_latency::total 941548961 # number of overall miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 183795 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::total 183795 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 183795 # number of demand (read+write) accesses
|
|
system.cpu.dtb_walker_cache.demand_accesses::total 183795 # number of demand (read+write) accesses
|
|
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 183795 # number of overall (read+write) accesses
|
|
system.cpu.dtb_walker_cache.overall_accesses::total 183795 # number of overall (read+write) accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429005 # miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429005 # miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429005 # miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429005 # miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429005 # miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429005 # miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11941.165532 # average ReadReq miss latency
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11941.165532 # average ReadReq miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11941.165532 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11941.165532 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11941.165532 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11941.165532 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dtb_walker_cache.writebacks::writebacks 22745 # number of writebacks
|
|
system.cpu.dtb_walker_cache.writebacks::total 22745 # number of writebacks
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 78849 # number of ReadReq MSHR misses
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 78849 # number of ReadReq MSHR misses
|
|
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 78849 # number of demand (read+write) MSHR misses
|
|
system.cpu.dtb_walker_cache.demand_mshr_misses::total 78849 # number of demand (read+write) MSHR misses
|
|
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 78849 # number of overall MSHR misses
|
|
system.cpu.dtb_walker_cache.overall_mshr_misses::total 78849 # number of overall MSHR misses
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 823159683 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 823159683 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 823159683 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 823159683 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 823159683 # number of overall MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 823159683 # number of overall MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429005 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429005 # mshr miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429005 # mshr miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average ReadReq mshr miss latency
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10439.697181 # average ReadReq mshr miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10439.697181 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10439.697181 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 996925 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 509.357790 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 8050243 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 997437 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 8.070929 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 148006664250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 509.357790 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.994839 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.994839 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 10113779 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 10113779 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 8050243 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 8050243 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 8050243 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 8050243 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 8050243 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 8050243 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1066046 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1066046 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1066046 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1066046 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1066046 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1066046 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14875004411 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 14875004411 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 14875004411 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 14875004411 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 14875004411 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 14875004411 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 9116289 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 9116289 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 9116289 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 9116289 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 9116289 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 9116289 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116939 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.116939 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.116939 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.116939 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.116939 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.116939 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13953.435791 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13953.435791 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13953.435791 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13953.435791 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13953.435791 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13953.435791 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 7127 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 341 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 20.900293 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68556 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 68556 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 68556 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 68556 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 68556 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 68556 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 997490 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 997490 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 997490 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 997490 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 997490 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 997490 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12688553873 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 12688553873 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12688553873 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 12688553873 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12688553873 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 12688553873 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109418 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.109418 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.109418 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12720.482284 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12720.482284 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12720.482284 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 12720.482284 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12720.482284 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 12720.482284 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.itb_walker_cache.tags.replacements 13512 # number of replacements
|
|
system.cpu.itb_walker_cache.tags.tagsinuse 6.614352 # Cycle average of tags in use
|
|
system.cpu.itb_walker_cache.tags.total_refs 26763 # Total number of references to valid blocks.
|
|
system.cpu.itb_walker_cache.tags.sampled_refs 13525 # Sample count of references to valid blocks.
|
|
system.cpu.itb_walker_cache.tags.avg_refs 1.978780 # Average number of references to valid blocks.
|
|
system.cpu.itb_walker_cache.tags.warmup_cycle 5101180103500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.614352 # Average occupied blocks per requestor
|
|
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.413397 # Average percentage of cache occupancy
|
|
system.cpu.itb_walker_cache.tags.occ_percent::total 0.413397 # Average percentage of cache occupancy
|
|
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
|
|
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
|
|
system.cpu.itb_walker_cache.tags.tag_accesses 96721 # Number of tag accesses
|
|
system.cpu.itb_walker_cache.tags.data_accesses 96721 # Number of data accesses
|
|
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26775 # number of ReadReq hits
|
|
system.cpu.itb_walker_cache.ReadReq_hits::total 26775 # number of ReadReq hits
|
|
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
|
|
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
|
|
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26777 # number of demand (read+write) hits
|
|
system.cpu.itb_walker_cache.demand_hits::total 26777 # number of demand (read+write) hits
|
|
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26777 # number of overall hits
|
|
system.cpu.itb_walker_cache.overall_hits::total 26777 # number of overall hits
|
|
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14389 # number of ReadReq misses
|
|
system.cpu.itb_walker_cache.ReadReq_misses::total 14389 # number of ReadReq misses
|
|
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14389 # number of demand (read+write) misses
|
|
system.cpu.itb_walker_cache.demand_misses::total 14389 # number of demand (read+write) misses
|
|
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14389 # number of overall misses
|
|
system.cpu.itb_walker_cache.overall_misses::total 14389 # number of overall misses
|
|
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 168738994 # number of ReadReq miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 168738994 # number of ReadReq miss cycles
|
|
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 168738994 # number of demand (read+write) miss cycles
|
|
system.cpu.itb_walker_cache.demand_miss_latency::total 168738994 # number of demand (read+write) miss cycles
|
|
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 168738994 # number of overall miss cycles
|
|
system.cpu.itb_walker_cache.overall_miss_latency::total 168738994 # number of overall miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41164 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::total 41164 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41166 # number of demand (read+write) accesses
|
|
system.cpu.itb_walker_cache.demand_accesses::total 41166 # number of demand (read+write) accesses
|
|
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41166 # number of overall (read+write) accesses
|
|
system.cpu.itb_walker_cache.overall_accesses::total 41166 # number of overall (read+write) accesses
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349553 # miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.349553 # miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349536 # miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.demand_miss_rate::total 0.349536 # miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349536 # miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.overall_miss_rate::total 0.349536 # miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11726.943776 # average ReadReq miss latency
|
|
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11726.943776 # average ReadReq miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11726.943776 # average overall miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11726.943776 # average overall miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11726.943776 # average overall miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11726.943776 # average overall miss latency
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.itb_walker_cache.writebacks::writebacks 3066 # number of writebacks
|
|
system.cpu.itb_walker_cache.writebacks::total 3066 # number of writebacks
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14389 # number of ReadReq MSHR misses
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14389 # number of ReadReq MSHR misses
|
|
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14389 # number of demand (read+write) MSHR misses
|
|
system.cpu.itb_walker_cache.demand_mshr_misses::total 14389 # number of demand (read+write) MSHR misses
|
|
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14389 # number of overall MSHR misses
|
|
system.cpu.itb_walker_cache.overall_mshr_misses::total 14389 # number of overall MSHR misses
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 147144512 # number of ReadReq MSHR miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 147144512 # number of ReadReq MSHR miss cycles
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 147144512 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 147144512 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 147144512 # number of overall MSHR miss cycles
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 147144512 # number of overall MSHR miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.349553 # mshr miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.349553 # mshr miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.349536 # mshr miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.349536 # mshr miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.349536 # mshr miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.349536 # mshr miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average ReadReq mshr miss latency
|
|
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10226.180555 # average ReadReq mshr miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10226.180555 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10226.180555 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 112729 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 64831.922119 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 3833002 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 176853 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 21.673378 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 50534.450143 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.577905 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 1.126849 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3105.817202 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 11175.950019 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.771095 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000222 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000017 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047391 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.170531 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.989257 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 64124 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 694 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3262 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7383 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52712 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978455 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 35081373 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 35081373 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68578 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12140 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 981027 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1334830 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2396575 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1586560 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 1586560 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 310 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 310 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 154702 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 154702 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 68578 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 12140 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 981027 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1489532 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2551277 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 68578 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 12140 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 981027 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1489532 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2551277 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 66 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 16363 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 35684 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 52120 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1439 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 1439 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 134046 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 134046 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 66 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 16363 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 169730 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 186166 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 66 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 16363 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 169730 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 186166 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6097000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 666500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1366410532 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3072121000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 4445295032 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22717321 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 22717321 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10374564266 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 10374564266 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6097000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 666500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1366410532 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 13446685266 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 14819859298 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6097000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 666500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1366410532 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 13446685266 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 14819859298 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68644 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12147 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 997390 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1370514 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 2448695 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1586560 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 1586560 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1749 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 1749 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 288748 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 288748 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68644 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 12147 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 997390 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1659262 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2737443 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68644 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 12147 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 997390 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1659262 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2737443 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000961 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000576 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016406 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026037 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.021285 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.822756 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.822756 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464232 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.464232 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000961 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000576 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016406 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102292 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.068007 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000961 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000576 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016406 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102292 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.068007 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 92378.787879 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 95214.285714 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83506.113304 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86092.394350 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 85289.620721 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15786.880473 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15786.880473 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77395.552765 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77395.552765 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92378.787879 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 95214.285714 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83506.113304 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79223.974937 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 79605.617019 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92378.787879 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 95214.285714 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83506.113304 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79223.974937 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 79605.617019 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 102850 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 102850 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 66 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16361 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35683 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 52117 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1439 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1439 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 134046 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 134046 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 66 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 16361 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 169729 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 186163 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 66 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 16361 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 169729 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 186163 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 604701 # number of ReadReq MSHR uncacheable
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 604701 # number of ReadReq MSHR uncacheable
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13919 # number of WriteReq MSHR uncacheable
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13919 # number of WriteReq MSHR uncacheable
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 618620 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 618620 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5264500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 578000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1161518218 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2626180250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3793540968 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 26446420 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 26446420 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8698623734 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8698623734 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5264500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 578000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1161518218 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11324803984 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 12492164702 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5264500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 578000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1161518218 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11324803984 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 12492164702 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88988446000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88988446000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2411352000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2411352000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91399798000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91399798000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026036 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021284 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.822756 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.822756 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464232 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464232 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102292 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.068006 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102292 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.068006 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70993.106656 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73597.518426 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72788.935817 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18378.332175 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18378.332175 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64892.825851 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64892.825851 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 147161.069686 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147161.069686 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173241.755873 # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173241.755873 # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 147747.887233 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 147747.887233 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 3067430 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 3066889 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 13919 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 13919 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 1586560 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46781 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2230 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 288754 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 288754 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::MessageReq 1643 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::BadAddressError 4 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1994880 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6121448 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 29602 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 170238 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 8316168 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63832960 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207882816 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 973632 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5848896 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 278538304 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 63315 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 5007317 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 3.009852 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.098766 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 4957986 99.01% 99.01% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 49331 0.99% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 5007317 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 4072528967 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 555000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1500637871 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 3138590336 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer2.occupancy 21588991 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer3.occupancy 118331389 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.trans_dist::ReadReq 223899 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 223899 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 57753 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 11033 # Transaction distribution
|
|
system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
|
|
system.iobus.trans_dist::MessageReq 1643 # Transaction distribution
|
|
system.iobus.trans_dist::MessageResp 1643 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 423734 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 468050 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95254 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95254 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 566590 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 211867 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 240311 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027800 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027800 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 3274683 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 3915016 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer9.occupancy 211868000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 257302678 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 457017000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 50364257 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 47572 # number of replacements
|
|
system.iocache.tags.tagsinuse 0.078977 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 4993305876000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.078977 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.004936 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.004936 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 428643 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 428643 # Number of data accesses
|
|
system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 907 # number of ReadReq misses
|
|
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
|
|
system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
|
|
system.iocache.demand_misses::pc.south_bridge.ide 907 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 907 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::pc.south_bridge.ide 907 # number of overall misses
|
|
system.iocache.overall_misses::total 907 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142095944 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 142095944 # number of ReadReq miss cycles
|
|
system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8602345477 # number of WriteInvalidateReq miss cycles
|
|
system.iocache.WriteInvalidateReq_miss_latency::total 8602345477 # number of WriteInvalidateReq miss cycles
|
|
system.iocache.demand_miss_latency::pc.south_bridge.ide 142095944 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 142095944 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::pc.south_bridge.ide 142095944 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 142095944 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::pc.south_bridge.ide 907 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 907 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::pc.south_bridge.ide 907 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 907 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 156665.869901 # average ReadReq miss latency
|
|
system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 184125.545313 # average WriteInvalidateReq miss latency
|
|
system.iocache.WriteInvalidateReq_avg_miss_latency::total 184125.545313 # average WriteInvalidateReq miss latency
|
|
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 156665.869901 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 156665.869901 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 29724 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 4480 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 6.634821 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 46667 # number of writebacks
|
|
system.iocache.writebacks::total 46667 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses
|
|
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
|
|
system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
|
|
system.iocache.demand_mshr_misses::pc.south_bridge.ide 907 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::pc.south_bridge.ide 907 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 907 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 94520448 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6172895487 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6172895487 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 94520448 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 94520448 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 104212.180816 # average ReadReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 132125.331485 # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 132125.331485 # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 104212.180816 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 104212.180816 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 657725 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 657721 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 13919 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 13919 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 149517 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 2208 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 1727 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 133760 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 133758 # Transaction distribution
|
|
system.membus.trans_dist::MessageReq 1643 # Transaction distribution
|
|
system.membus.trans_dist::MessageResp 1643 # Transaction distribution
|
|
system.membus.trans_dist::BadAddressError 4 # Transaction distribution
|
|
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 468050 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769190 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477841 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 8 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1715089 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141457 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 141457 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1859832 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 240311 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538377 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18435328 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20214016 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 26225708 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 1635 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 1005577 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1.001634 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0.040388 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 1003934 99.84% 99.84% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 1643 0.16% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 1005577 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 357821000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 388531000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer3.occupancy 1203162900 # Layer occupancy (ticks)
|
|
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer4.occupancy 5000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks)
|
|
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 2211768878 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer4.occupancy 51465743 # Layer occupancy (ticks)
|
|
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
|
|
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
|
|
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
|
|
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
|
|
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
|
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|