4b256577e0
cpu/base_dyn_inst.cc:
cpu/o3/bpred_unit.hh:
cpu/o3/comm.hh:
cpu/o3/cpu.hh:
cpu/o3/regfile.hh:
cpu/ozone/cpu_impl.hh:
cpu/ozone/ea_list.cc:
cpu/ozone/ea_list.hh:
kern/kernel_stats.cc:
Changed arch/alpha to targetarch
sim/process.cc:
Changed arch/alpha to targetarch, and removed gaurding ifdef
--HG--
extra : convert_revision : 3c29e6baeb1cd900f7b5e11144a5d547a6c7c5ab
72 lines
2.8 KiB
C++
72 lines
2.8 KiB
C++
/*
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* Copyright (c) 2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_EA_LIST_HH__
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#define __CPU_EA_LIST_HH__
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#include <list>
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#include <utility>
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#include "targetarch/isa_traits.hh"
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#include "cpu/inst_seq.hh"
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/**
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* Simple class to hold onto a list of pairs, each pair having a memory
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* instruction's sequence number and effective addr. This list can be used
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* for memory disambiguation. However, if I ever want to forward results, I
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* may have to use a list that holds DynInstPtrs. Hence this may change in
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* the future.
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*/
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class EAList {
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private:
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typedef std::pair<InstSeqNum, Addr> instEA;
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typedef std::list<instEA>::iterator eaListIt;
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typedef std::list<instEA>::const_iterator constEAListIt;
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std::list<instEA> eaList;
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public:
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EAList() { }
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~EAList() { }
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void addAddr(const InstSeqNum &new_sn, const Addr &new_ea);
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void clearAddr(const InstSeqNum &sn_to_clear, const Addr &ea_to_clear);
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/** Checks if any instructions older than check_sn have a conflicting
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* address with check_ea. Note that this function does not handle the
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* sequence number rolling over.
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*/
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bool checkConflict(const InstSeqNum &check_sn, const Addr &check_ea) const;
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void clear();
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void commit(const InstSeqNum &commit_sn);
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};
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#endif // __CPU_EA_LIST_HH__
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