Andreas Hansson 2208ea049f MEM: Make the bus bridge unidirectional and fixed address range ... This patch makes the bus bridge uni-directional and specialises the bus ports to be a master port and a slave port. This greatly simplifies the assumptions on both sides as either port only has to deal with requests or responses. The following patches introduce the notion of master and slave ports, and would not be possible without this split of responsibilities. In making the bridge unidirectional, the address range mechanism of the bridge is also changed. For the cases where communication is taking place both ways, an additional bridge is needed. This causes issues with the existing mechanism, as the busses cannot determine when to stop iterating the address updates from the two bridges. To avoid this issue, and also greatly simplify the specification, the bridge now has a fixed set of address ranges, specified at creation time.		2012-01-17 12:55:09 -06:00
..
inorder-timing.py	MEM: Add port proxies instead of non-structural ports	2012-01-17 12:55:08 -06:00
memtest-ruby.py	MEM: Add port proxies instead of non-structural ports	2012-01-17 12:55:08 -06:00
memtest.py	MEM: Add port proxies instead of non-structural ports	2012-01-17 12:55:08 -06:00
o3-timing-mp-ruby.py	Config: Keep track of uncached and cached ports separately.	2011-02-03 20:23:00 -08:00
o3-timing-mp.py	MEM: Add port proxies instead of non-structural ports	2012-01-17 12:55:08 -06:00
o3-timing-ruby.py	Config: Keep track of uncached and cached ports separately.	2011-02-03 20:23:00 -08:00
o3-timing.py	MEM: Add port proxies instead of non-structural ports	2012-01-17 12:55:08 -06:00
pc-o3-timing.py	MEM: Make the bus bridge unidirectional and fixed address range	2012-01-17 12:55:09 -06:00
pc-simple-atomic.py	MEM: Make the bus bridge unidirectional and fixed address range	2012-01-17 12:55:09 -06:00
pc-simple-timing.py	MEM: Make the bus bridge unidirectional and fixed address range	2012-01-17 12:55:09 -06:00
realview-o3-dual.py	MEM: Make the bus bridge unidirectional and fixed address range	2012-01-17 12:55:09 -06:00
realview-o3.py	MEM: Make the bus bridge unidirectional and fixed address range	2012-01-17 12:55:09 -06:00
realview-simple-atomic-dual.py	MEM: Make the bus bridge unidirectional and fixed address range	2012-01-17 12:55:09 -06:00
realview-simple-atomic.py	MEM: Make the bus bridge unidirectional and fixed address range	2012-01-17 12:55:09 -06:00
realview-simple-timing-dual.py	MEM: Make the bus bridge unidirectional and fixed address range	2012-01-17 12:55:09 -06:00
realview-simple-timing.py	MEM: Make the bus bridge unidirectional and fixed address range	2012-01-17 12:55:09 -06:00
rubytest-ruby.py	MEM: Add port proxies instead of non-structural ports	2012-01-17 12:55:08 -06:00
simple-atomic-mp-ruby.py	Config: Keep track of uncached and cached ports separately.	2011-02-03 20:23:00 -08:00
simple-atomic-mp.py	MEM: Add port proxies instead of non-structural ports	2012-01-17 12:55:08 -06:00
simple-atomic.py	MEM: Add port proxies instead of non-structural ports	2012-01-17 12:55:08 -06:00
simple-timing-mp-ruby.py	MEM: Add port proxies instead of non-structural ports	2012-01-17 12:55:08 -06:00
simple-timing-mp.py	MEM: Add port proxies instead of non-structural ports	2012-01-17 12:55:08 -06:00
simple-timing-ruby.py	MEM: Add port proxies instead of non-structural ports	2012-01-17 12:55:08 -06:00
simple-timing.py	MEM: Add port proxies instead of non-structural ports	2012-01-17 12:55:08 -06:00
t1000-simple-atomic.py	Config: Keep track of uncached and cached ports separately.	2011-02-03 20:23:00 -08:00
tsunami-inorder.py	MEM: Make the bus bridge unidirectional and fixed address range	2012-01-17 12:55:09 -06:00
tsunami-o3-dual.py	MEM: Make the bus bridge unidirectional and fixed address range	2012-01-17 12:55:09 -06:00
tsunami-o3.py	MEM: Make the bus bridge unidirectional and fixed address range	2012-01-17 12:55:09 -06:00
tsunami-simple-atomic-dual.py	MEM: Make the bus bridge unidirectional and fixed address range	2012-01-17 12:55:09 -06:00
tsunami-simple-atomic.py	MEM: Make the bus bridge unidirectional and fixed address range	2012-01-17 12:55:09 -06:00
tsunami-simple-timing-dual.py	MEM: Make the bus bridge unidirectional and fixed address range	2012-01-17 12:55:09 -06:00
tsunami-simple-timing.py	MEM: Make the bus bridge unidirectional and fixed address range	2012-01-17 12:55:09 -06:00
twosys-tsunami-simple-atomic.py	MEM: Make the bus bridge unidirectional and fixed address range	2012-01-17 12:55:09 -06:00