6629d9b2bc
Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus.
73 lines
3.2 KiB
Python
73 lines
3.2 KiB
Python
# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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from m5.params import *
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from m5.proxy import *
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from MemObject import MemObject
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class PioDevice(MemObject):
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type = 'PioDevice'
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abstract = True
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pio = Port("Programmed I/O port")
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platform = Param.Platform(Parent.any, "Platform this device is part of")
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system = Param.System(Parent.any, "System this device is part of")
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class BasicPioDevice(PioDevice):
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type = 'BasicPioDevice'
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abstract = True
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pio_addr = Param.Addr("Device Address")
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pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
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class DmaDevice(PioDevice):
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type = 'DmaDevice'
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abstract = True
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dma = Port(Self.pio.peerObj.port, "DMA port")
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min_backoff_delay = Param.Latency('4ns',
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"min time between a nack packet being received and the next request made by the device")
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max_backoff_delay = Param.Latency('10us',
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"max time between a nack packet being received and the next request made by the device")
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class IsaFake(BasicPioDevice):
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type = 'IsaFake'
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pio_size = Param.Addr(0x8, "Size of address range")
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ret_data8 = Param.UInt8(0xFF, "Default data to return")
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ret_data16 = Param.UInt16(0xFFFF, "Default data to return")
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ret_data32 = Param.UInt32(0xFFFFFFFF, "Default data to return")
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ret_data64 = Param.UInt64(0xFFFFFFFFFFFFFFFF, "Default data to return")
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ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access")
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update_data = Param.Bool(False, "Update the data that is returned on writes")
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warn_access = Param.String("", "String to print when device is accessed")
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class BadAddr(IsaFake):
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pio_addr = 0
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ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access")
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