4a5b51b516
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem SConstruct: src/SConscript: src/arch/SConscript: src/arch/alpha/faults.cc: src/arch/alpha/tlb.cc: src/base/traceflags.py: src/cpu/SConscript: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.cc: src/cpu/cpu_exec_context.cc: src/cpu/cpu_exec_context.hh: src/cpu/exec_context.hh: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/regfile.hh: src/cpu/ozone/cpu.hh: src/cpu/simple/base.cc: src/cpu/base_dyn_inst.hh: src/cpu/o3/2bit_local_pred.cc: src/cpu/o3/2bit_local_pred.hh: src/cpu/o3/alpha_cpu.cc: src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_dyn_inst.cc: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/alpha_impl.hh: src/cpu/o3/alpha_params.hh: src/cpu/o3/bpred_unit.cc: src/cpu/o3/bpred_unit.hh: src/cpu/o3/bpred_unit_impl.hh: src/cpu/o3/btb.cc: src/cpu/o3/btb.hh: src/cpu/o3/comm.hh: src/cpu/o3/commit.cc: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu_policy.hh: src/cpu/o3/decode.cc: src/cpu/o3/decode.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch.cc: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/free_list.cc: src/cpu/o3/free_list.hh: src/cpu/o3/iew.cc: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.cc: src/cpu/o3/inst_queue.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/mem_dep_unit.cc: src/cpu/o3/mem_dep_unit.hh: src/cpu/o3/mem_dep_unit_impl.hh: src/cpu/o3/ras.cc: src/cpu/o3/ras.hh: src/cpu/o3/rename.cc: src/cpu/o3/rename.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/rename_map.cc: src/cpu/o3/rename_map.hh: src/cpu/o3/rob.cc: src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: src/cpu/o3/sat_counter.cc: src/cpu/o3/sat_counter.hh: src/cpu/o3/store_set.cc: src/cpu/o3/store_set.hh: src/cpu/o3/tournament_pred.cc: src/cpu/o3/tournament_pred.hh: Hand merges. --HG-- rename : build/SConstruct => SConstruct rename : SConscript => src/SConscript rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa rename : arch/alpha/isa/pal.isa => src/arch/alpha/isa/pal.isa rename : base/traceflags.py => src/base/traceflags.py rename : cpu/SConscript => src/cpu/SConscript rename : cpu/base.cc => src/cpu/base.cc rename : cpu/base.hh => src/cpu/base.hh rename : cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst.cc rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh rename : cpu/cpu_exec_context.cc => src/cpu/cpu_exec_context.cc rename : cpu/cpu_exec_context.hh => src/cpu/cpu_exec_context.hh rename : cpu/cpu_models.py => src/cpu/cpu_models.py rename : cpu/exec_context.hh => src/cpu/exec_context.hh rename : cpu/exetrace.cc => src/cpu/exetrace.cc rename : cpu/exetrace.hh => src/cpu/exetrace.hh rename : cpu/inst_seq.hh => src/cpu/inst_seq.hh rename : cpu/o3/2bit_local_pred.cc => src/cpu/o3/2bit_local_pred.cc rename : cpu/o3/2bit_local_pred.hh => src/cpu/o3/2bit_local_pred.hh rename : cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha_cpu.hh rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha_cpu_builder.cc rename : cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha_cpu_impl.hh rename : cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha_dyn_inst.hh rename : cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha_dyn_inst_impl.hh rename : cpu/o3/alpha_impl.hh => src/cpu/o3/alpha_impl.hh rename : cpu/o3/alpha_params.hh => src/cpu/o3/alpha_params.hh rename : cpu/o3/bpred_unit.cc => src/cpu/o3/bpred_unit.cc rename : cpu/o3/bpred_unit.hh => src/cpu/o3/bpred_unit.hh rename : cpu/o3/bpred_unit_impl.hh => src/cpu/o3/bpred_unit_impl.hh rename : cpu/o3/btb.cc => src/cpu/o3/btb.cc rename : cpu/o3/btb.hh => src/cpu/o3/btb.hh rename : cpu/o3/comm.hh => src/cpu/o3/comm.hh rename : cpu/o3/commit.cc => src/cpu/o3/commit.cc rename : cpu/o3/commit.hh => src/cpu/o3/commit.hh rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc rename : cpu/o3/cpu.hh => src/cpu/o3/cpu.hh rename : cpu/o3/cpu_policy.hh => src/cpu/o3/cpu_policy.hh rename : cpu/o3/decode.cc => src/cpu/o3/decode.cc rename : cpu/o3/decode.hh => src/cpu/o3/decode.hh rename : cpu/o3/decode_impl.hh => src/cpu/o3/decode_impl.hh rename : cpu/o3/fetch.cc => src/cpu/o3/fetch.cc rename : cpu/o3/fetch.hh => src/cpu/o3/fetch.hh rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh rename : cpu/o3/free_list.cc => src/cpu/o3/free_list.cc rename : cpu/o3/free_list.hh => src/cpu/o3/free_list.hh rename : cpu/o3/iew.cc => src/cpu/o3/iew.cc rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh rename : cpu/o3/inst_queue.cc => src/cpu/o3/inst_queue.cc rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh rename : cpu/o3/mem_dep_unit.cc => src/cpu/o3/mem_dep_unit.cc rename : cpu/o3/mem_dep_unit.hh => src/cpu/o3/mem_dep_unit.hh rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh rename : cpu/o3/ras.cc => src/cpu/o3/ras.cc rename : cpu/o3/ras.hh => src/cpu/o3/ras.hh rename : cpu/o3/regfile.hh => src/cpu/o3/regfile.hh rename : cpu/o3/rename.cc => src/cpu/o3/rename.cc rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh rename : cpu/o3/rename_map.cc => src/cpu/o3/rename_map.cc rename : cpu/o3/rename_map.hh => src/cpu/o3/rename_map.hh rename : cpu/o3/rob.hh => src/cpu/o3/rob.hh rename : cpu/o3/rob_impl.hh => src/cpu/o3/rob_impl.hh rename : cpu/o3/sat_counter.hh => src/cpu/o3/sat_counter.hh rename : cpu/o3/store_set.cc => src/cpu/o3/store_set.cc rename : cpu/o3/store_set.hh => src/cpu/o3/store_set.hh rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh rename : cpu/ozone/cpu.cc => src/cpu/ozone/cpu.cc rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh rename : cpu/static_inst.hh => src/cpu/static_inst.hh rename : kern/system_events.cc => src/kern/system_events.cc rename : kern/tru64/tru64.hh => src/kern/tru64/tru64.hh rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaFullCPU.py rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc extra : convert_revision : ff351fc0e3a7c0f23e59fdbec33d8209eb9280be
226 lines
7.6 KiB
C++
226 lines
7.6 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_BPRED_UNIT_HH__
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#define __CPU_O3_BPRED_UNIT_HH__
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// For Addr type.
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#include "arch/isa_traits.hh"
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#include "base/statistics.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/o3/2bit_local_pred.hh"
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#include "cpu/o3/btb.hh"
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#include "cpu/o3/ras.hh"
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#include "cpu/o3/tournament_pred.hh"
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#include <list>
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/**
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* Basically a wrapper class to hold both the branch predictor
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* and the BTB.
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*/
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template<class Impl>
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class TwobitBPredUnit
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{
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public:
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typedef typename Impl::Params Params;
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typedef typename Impl::DynInstPtr DynInstPtr;
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/**
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* @param params The params object, that has the size of the BP and BTB.
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*/
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TwobitBPredUnit(Params *params);
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/**
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* Registers statistics.
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*/
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void regStats();
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void switchOut();
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void takeOverFrom();
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/**
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* Predicts whether or not the instruction is a taken branch, and the
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* target of the branch if it is taken.
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* @param inst The branch instruction.
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* @param PC The predicted PC is passed back through this parameter.
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* @param tid The thread id.
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* @return Returns if the branch is taken or not.
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*/
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bool predict(DynInstPtr &inst, Addr &PC, unsigned tid);
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/**
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* Tells the branch predictor to commit any updates until the given
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* sequence number.
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* @param done_sn The sequence number to commit any older updates up until.
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* @param tid The thread id.
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*/
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void update(const InstSeqNum &done_sn, unsigned tid);
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/**
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* Squashes all outstanding updates until a given sequence number.
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* @param squashed_sn The sequence number to squash any younger updates up
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* until.
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* @param tid The thread id.
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*/
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void squash(const InstSeqNum &squashed_sn, unsigned tid);
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/**
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* Squashes all outstanding updates until a given sequence number, and
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* corrects that sn's update with the proper address and taken/not taken.
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* @param squashed_sn The sequence number to squash any younger updates up
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* until.
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* @param corr_target The correct branch target.
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* @param actually_taken The correct branch direction.
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* @param tid The thread id.
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*/
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void squash(const InstSeqNum &squashed_sn, const Addr &corr_target,
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bool actually_taken, unsigned tid);
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/**
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* Looks up a given PC in the BP to see if it is taken or not taken.
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* @param inst_PC The PC to look up.
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* @return Whether the branch is taken or not taken.
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*/
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bool BPLookup(Addr &inst_PC)
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{ return BP.lookup(inst_PC); }
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/**
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* Looks up a given PC in the BTB to see if a matching entry exists.
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* @param inst_PC The PC to look up.
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* @return Whether the BTB contains the given PC.
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*/
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bool BTBValid(Addr &inst_PC)
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{ return BTB.valid(inst_PC, 0); }
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/**
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* Looks up a given PC in the BTB to get the predicted target.
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* @param inst_PC The PC to look up.
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* @return The address of the target of the branch.
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*/
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Addr BTBLookup(Addr &inst_PC)
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{ return BTB.lookup(inst_PC, 0); }
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/**
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* Updates the BP with taken/not taken information.
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* @param inst_PC The branch's PC that will be updated.
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* @param taken Whether the branch was taken or not taken.
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* @todo Make this update flexible enough to handle a global predictor.
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*/
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void BPUpdate(Addr &inst_PC, bool taken)
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{ BP.update(inst_PC, taken); }
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/**
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* Updates the BTB with the target of a branch.
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* @param inst_PC The branch's PC that will be updated.
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* @param target_PC The branch's target that will be added to the BTB.
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*/
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void BTBUpdate(Addr &inst_PC, Addr &target_PC)
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{ BTB.update(inst_PC, target_PC,0); }
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private:
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struct PredictorHistory {
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/**
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* Makes a predictor history struct that contains a sequence number,
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* the PC of its instruction, and whether or not it was predicted
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* taken.
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*/
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PredictorHistory(const InstSeqNum &seq_num, const Addr &inst_PC,
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const bool pred_taken, const unsigned _tid)
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: seqNum(seq_num), PC(inst_PC), RASTarget(0), globalHistory(0),
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RASIndex(0), tid(_tid), predTaken(pred_taken), usedRAS(0),
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wasCall(0)
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{ }
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/** The sequence number for the predictor history entry. */
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InstSeqNum seqNum;
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/** The PC associated with the sequence number. */
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Addr PC;
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/** The RAS target (only valid if a return). */
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Addr RASTarget;
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/** The global history at the time this entry was created. */
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unsigned globalHistory;
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/** The RAS index of the instruction (only valid if a call). */
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unsigned RASIndex;
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/** The thread id. */
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unsigned tid;
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/** Whether or not it was predicted taken. */
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bool predTaken;
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/** Whether or not the RAS was used. */
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bool usedRAS;
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/** Whether or not the instruction was a call. */
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bool wasCall;
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};
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typedef std::list<PredictorHistory> History;
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/**
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* The per-thread predictor history. This is used to update the predictor
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* as instructions are committed, or restore it to the proper state after
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* a squash.
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*/
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History predHist[Impl::MaxThreads];
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/** The branch predictor. */
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DefaultBP BP;
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/** The BTB. */
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DefaultBTB BTB;
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/** The per-thread return address stack. */
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ReturnAddrStack RAS[Impl::MaxThreads];
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/** Stat for number of BP lookups. */
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Stats::Scalar<> lookups;
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/** Stat for number of conditional branches predicted. */
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Stats::Scalar<> condPredicted;
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/** Stat for number of conditional branches predicted incorrectly. */
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Stats::Scalar<> condIncorrect;
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/** Stat for number of BTB lookups. */
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Stats::Scalar<> BTBLookups;
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/** Stat for number of BTB hits. */
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Stats::Scalar<> BTBHits;
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/** Stat for number of times the BTB is correct. */
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Stats::Scalar<> BTBCorrect;
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/** Stat for number of times the RAS is used to get a target. */
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Stats::Scalar<> usedRAS;
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/** Stat for number of times the RAS is incorrect. */
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Stats::Scalar<> RASIncorrect;
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};
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#endif // __CPU_O3_BPRED_UNIT_HH__
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