716ceb6c10
arch/alpha/isa_traits.hh: Add in clear functions. cpu/base.cc: cpu/base.hh: Add in CPU progress event. cpu/base_dyn_inst.hh: Mimic normal registers in terms of writing/reading floats. cpu/checker/cpu.cc: cpu/checker/cpu.hh: cpu/checker/cpu_builder.cc: cpu/checker/o3_cpu_builder.cc: Fix up stuff. cpu/cpu_exec_context.cc: cpu/cpu_exec_context.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: Bring up to speed with newmem. cpu/o3/alpha_cpu_builder.cc: Allow for progress intervals. cpu/o3/tournament_pred.cc: Fix up predictor. cpu/o3/tournament_pred.hh: cpu/ozone/cpu.hh: cpu/ozone/cpu_impl.hh: cpu/simple/cpu.cc: Fixes. cpu/ozone/cpu_builder.cc: Allow progress interval. cpu/ozone/front_end_impl.hh: Comment out this message. cpu/ozone/lw_back_end_impl.hh: Remove this. python/m5/objects/BaseCPU.py: Add progress interval. python/m5/objects/Root.py: Allow for stat reset. sim/serialize.cc: sim/stat_control.cc: Add in stats reset. --HG-- extra : convert_revision : fdb5ac5542099173cc30c40ea93372a065534b5e
357 lines
9.3 KiB
C++
357 lines
9.3 KiB
C++
/*
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* Copyright (c) 2001-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <string>
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#include "cpu/base.hh"
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#include "cpu/cpu_exec_context.hh"
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#include "cpu/exec_context.hh"
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#if FULL_SYSTEM
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#include "base/callback.hh"
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#include "base/cprintf.hh"
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#include "base/output.hh"
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#include "base/trace.hh"
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#include "cpu/profile.hh"
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#include "cpu/quiesce_event.hh"
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#include "kern/kernel_stats.hh"
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#include "sim/serialize.hh"
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#include "sim/sim_exit.hh"
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#include "sim/system.hh"
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#include "arch/stacktrace.hh"
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#else
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#include "sim/process.hh"
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#endif
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using namespace std;
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// constructor
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#if FULL_SYSTEM
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CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
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AlphaITB *_itb, AlphaDTB *_dtb,
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FunctionalMemory *_mem,
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bool use_kernel_stats)
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: _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
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cpu_id(-1), lastActivate(0), lastSuspend(0), mem(_mem), itb(_itb),
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dtb(_dtb), system(_sys), memctrl(_sys->memctrl), physmem(_sys->physmem),
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profile(NULL), func_exe_inst(0), storeCondFailures(0)
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{
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proxy = new ProxyExecContext<CPUExecContext>(this);
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quiesceEvent = new EndQuiesceEvent(proxy);
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memset(®s, 0, sizeof(RegFile));
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if (cpu->params->profile) {
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profile = new FunctionProfile(system->kernelSymtab);
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Callback *cb =
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new MakeCallback<CPUExecContext,
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&CPUExecContext::dumpFuncProfile>(this);
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registerExitCallback(cb);
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}
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// let's fill with a dummy node for now so we don't get a segfault
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// on the first cycle when there's no node available.
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static ProfileNode dummyNode;
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profileNode = &dummyNode;
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profilePC = 3;
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if (use_kernel_stats) {
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kernelStats = new Kernel::Statistics(system);
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} else {
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kernelStats = NULL;
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}
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}
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#else
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CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num,
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Process *_process, int _asid)
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: _status(ExecContext::Unallocated),
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cpu(_cpu), thread_num(_thread_num), cpu_id(-1), lastActivate(0),
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lastSuspend(0), process(_process), mem(process->getMemory()), asid(_asid),
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func_exe_inst(0), storeCondFailures(0)
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{
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memset(®s, 0, sizeof(RegFile));
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proxy = new ProxyExecContext<CPUExecContext>(this);
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}
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CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num,
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FunctionalMemory *_mem, int _asid)
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: cpu(_cpu), thread_num(_thread_num), process(0), mem(_mem), asid(_asid),
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func_exe_inst(0), storeCondFailures(0)
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{
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memset(®s, 0, sizeof(RegFile));
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proxy = new ProxyExecContext<CPUExecContext>(this);
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}
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CPUExecContext::CPUExecContext(RegFile *regFile)
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: cpu(NULL), thread_num(-1), process(NULL), mem(NULL), asid(-1),
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func_exe_inst(0), storeCondFailures(0)
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{
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regs = *regFile;
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proxy = new ProxyExecContext<CPUExecContext>(this);
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}
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#endif
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CPUExecContext::CPUExecContext()
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#if !FULL_SYSTEM
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: cpu(NULL), thread_num(-1), process(NULL), mem(NULL), asid(-1),
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func_exe_inst(0), storeCondFailures(0)
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#else
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: cpu(NULL), thread_num(-1), cpu_id(-1), lastActivate(0), lastSuspend(0),
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mem(NULL), itb(NULL), dtb(NULL), system(NULL), memctrl(NULL),
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physmem(NULL), profile(NULL), func_exe_inst(0), storeCondFailures(0)
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#endif
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{
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regs.clear();
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proxy = new ProxyExecContext<CPUExecContext>(this);
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}
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CPUExecContext::~CPUExecContext()
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{
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delete proxy;
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}
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#if FULL_SYSTEM
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void
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CPUExecContext::dumpFuncProfile()
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{
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std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
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profile->dump(proxy, *os);
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}
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void
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CPUExecContext::profileClear()
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{
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if (profile)
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profile->clear();
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}
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void
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CPUExecContext::profileSample()
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{
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if (profile)
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profile->sample(profileNode, profilePC);
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}
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#endif
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void
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CPUExecContext::takeOverFrom(ExecContext *oldContext)
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{
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// some things should already be set up
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assert(mem == oldContext->getMemPtr());
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#if FULL_SYSTEM
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assert(system == oldContext->getSystemPtr());
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#else
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assert(process == oldContext->getProcessPtr());
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#endif
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copyState(oldContext);
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#if FULL_SYSTEM
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EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
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if (quiesce) {
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// Point the quiesce event's XC at this XC so that it wakes up
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// the proper CPU.
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quiesce->xc = proxy;
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}
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if (quiesceEvent) {
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quiesceEvent->xc = proxy;
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}
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#endif
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storeCondFailures = 0;
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oldContext->setStatus(ExecContext::Unallocated);
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}
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void
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CPUExecContext::copyXC(ExecContext *context)
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{
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copyState(context);
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#if FULL_SYSTEM
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EndQuiesceEvent *quiesce = context->getQuiesceEvent();
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if (quiesce) {
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quiesceEvent = quiesce;
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}
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Kernel::Statistics *stats = context->getKernelStats();
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if (stats) {
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kernelStats = stats;
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}
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#endif
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}
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void
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CPUExecContext::copyState(ExecContext *oldContext)
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{
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// copy over functional state
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_status = oldContext->status();
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copyArchRegs(oldContext);
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cpu_id = oldContext->readCpuId();
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#if !FULL_SYSTEM
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func_exe_inst = oldContext->readFuncExeInst();
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#endif
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inst = oldContext->getInst();
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}
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void
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CPUExecContext::serialize(ostream &os)
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{
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SERIALIZE_ENUM(_status);
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regs.serialize(os);
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// thread_num and cpu_id are deterministic from the config
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SERIALIZE_SCALAR(func_exe_inst);
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SERIALIZE_SCALAR(inst);
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#if FULL_SYSTEM
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Tick quiesceEndTick = 0;
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if (quiesceEvent->scheduled())
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quiesceEndTick = quiesceEvent->when();
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SERIALIZE_SCALAR(quiesceEndTick);
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if (kernelStats)
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kernelStats->serialize(os);
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#endif
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}
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void
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CPUExecContext::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_ENUM(_status);
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regs.unserialize(cp, section);
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// thread_num and cpu_id are deterministic from the config
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UNSERIALIZE_SCALAR(func_exe_inst);
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UNSERIALIZE_SCALAR(inst);
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#if FULL_SYSTEM
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Tick quiesceEndTick;
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UNSERIALIZE_SCALAR(quiesceEndTick);
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if (quiesceEndTick)
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quiesceEvent->schedule(quiesceEndTick);
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if (kernelStats)
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kernelStats->unserialize(cp, section);
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#endif
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}
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void
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CPUExecContext::activate(int delay)
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{
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if (status() == ExecContext::Active)
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return;
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lastActivate = curTick;
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if (status() == ExecContext::Unallocated) {
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cpu->activateWhenReady(thread_num);
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return;
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}
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_status = ExecContext::Active;
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// status() == Suspended
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cpu->activateContext(thread_num, delay);
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}
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void
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CPUExecContext::suspend()
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{
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if (status() == ExecContext::Suspended)
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return;
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lastActivate = curTick;
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lastSuspend = curTick;
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/*
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#if FULL_SYSTEM
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// Don't change the status from active if there are pending interrupts
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if (cpu->check_interrupts()) {
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assert(status() == ExecContext::Active);
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return;
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}
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#endif
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*/
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_status = ExecContext::Suspended;
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cpu->suspendContext(thread_num);
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}
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void
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CPUExecContext::deallocate()
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{
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if (status() == ExecContext::Unallocated)
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return;
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_status = ExecContext::Unallocated;
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cpu->deallocateContext(thread_num);
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}
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void
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CPUExecContext::halt()
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{
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if (status() == ExecContext::Halted)
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return;
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_status = ExecContext::Halted;
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cpu->haltContext(thread_num);
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}
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void
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CPUExecContext::regStats(const string &name)
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{
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#if FULL_SYSTEM
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if (kernelStats)
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kernelStats->regStats(name + ".kern");
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#endif
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}
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void
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CPUExecContext::copyArchRegs(ExecContext *xc)
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{
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TheISA::copyRegs(xc, proxy);
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/*
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// First loop through the integer registers.
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for (int i = 0; i < AlphaISA::NumIntRegs; ++i) {
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setIntReg(i, xc->readIntReg(i));
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}
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// Then loop through the floating point registers.
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for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) {
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setFloatRegDouble(i, xc->readFloatRegDouble(i));
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setFloatRegInt(i, xc->readFloatRegInt(i));
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}
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// Copy misc. registers
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TheISA::copyMiscRegs(xc, proxy);
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// Lastly copy PC/NPC
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setPC(xc->readPC());
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setNextPC(xc->readNextPC());
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*/
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}
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