b38f67d5b7
requestTime -> time
responseTime -> packet.time
Make CPU and memory able to connect to the bus
dev/io_device.cc:
update for request and packet both having a time
hand platform off to port for eventual selection of request modes
dev/io_device.hh:
update for request and packet both havig a time
hand platform off to port for eventual selection of request modes
mem/bus.hh:
Add a device map struct that maps a range to a portId
- Which needs work it theory it should be an interval tree
- but it is a list and works fine right now
Add a function called findPort which returns port for an addr range
Add a deviceBlockSize function that really shouldn't exist, but it
was easier than fixing the translating port
mem/packet.hh:
add a time to each packet
mem/physical.cc:
mem/physical.hh:
python/m5/objects/PhysicalMemory.py:
Make physical memory take a MemObject parameter of what to connect to
mem/request.hh:
remove requestTime/responseTime for just time in request which
is requset time and the time in the packet which is responsetime
python/m5/objects/BaseCPU.py:
Instead of memory cpu connects to any memory object
python/m5/objects/Bus.py:
Fix for new bus object
--HG--
extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d
129 lines
4.4 KiB
C++
129 lines
4.4 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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* Declaration of the Packet Class, a packet is a transaction occuring
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* between a single level of the memory heirarchy (ie L1->L2).
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*/
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#ifndef __MEM_PACKET_HH__
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#define __MEM_PACKET_HH__
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#include "mem/request.hh"
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#include "arch/isa_traits.hh"
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#include "sim/root.hh"
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struct Packet;
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typedef Packet* PacketPtr;
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typedef uint8_t* PacketDataPtr;
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/** List of all commands associated with a packet. */
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enum Command
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{
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Read,
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Write
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};
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/** The result of a particular pakets request. */
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enum PacketResult
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{
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Success,
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BadAddress,
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Unknown
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};
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class SenderState{};
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class Coherence{};
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/**
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* A Packet is the structure to handle requests between two levels
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* of the memory system. The Request is a global object that trancends
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* all of the memory heirarchy, but at each levels interface a packet
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* is created to transfer data/requests. For example, a request would
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* be used to initiate a request to go to memory/IOdevices, as the request
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* passes through the memory system several packets will be created. One
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* will be created to go between the L1 and L2 caches and another to go to
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* the next level and so forth.
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*
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* Packets are assumed to be returned in the case of a single response. If
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* the transaction has no response, then the consumer will delete the packet.
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*/
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struct Packet
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{
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/** The address of the request, could be virtual or physical (depending on
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cache configurations). */
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Addr addr;
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/** Flag structure to hold flags for this particular packet */
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uint64_t flags;
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/** A pointer to the overall request. */
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RequestPtr req;
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/** A virtual base opaque structure used to hold
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coherence status messages. */
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Coherence *coherence; // virtual base opaque,
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// assert(dynamic_cast<Foo>) etc.
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/** A virtual base opaque structure used to hold the senders state. */
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SenderState *senderState; // virtual base opaque,
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// assert(dynamic_cast<Foo>) etc.
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/** A pointer to the data being transfered. It can be differnt sizes
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at each level of the heirarchy so it belongs in the packet,
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not request*/
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PacketDataPtr data;
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/** Indicates the size of the request. */
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int size;
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/** A index of the source of the transaction. */
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short src;
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/** A index to the destination of the transaction. */
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short dest;
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/** The command of the transaction. */
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Command cmd;
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/** The time this request was responded to. Used to calculate latencies. */
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Tick time;
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/** The result of the packet transaction. */
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PacketResult result;
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/** Accessor function that returns the source index of the packet. */
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short getSrc() const { return src; }
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/** Accessor function that returns the destination index of
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the packet. */
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short getDest() const { return dest; }
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};
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#endif //__MEM_PACKET_HH
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