240 lines
7.2 KiB
C++
240 lines
7.2 KiB
C++
// Copyright (c) 2015 ARM Limited
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// All rights reserved.
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// Copyright 2009-2014 Sandia Coporation. Under the terms
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// of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S.
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// Government retains certain rights in this software.
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//
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// Copyright (c) 2009-2014, Sandia Corporation
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// All rights reserved.
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//
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// For license information, see the LICENSE file in the current directory.
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#include "gem5.hh"
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#ifdef fatal // gem5 sets this
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#undef fatal
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#endif
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#include <sst_config.h>
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#include <mem/packet.hh>
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#include <sst/core/component.h>
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#include <sst/core/params.h>
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#include <sst/core/link.h>
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#include <sst/elements/memHierarchy/memNIC.h>
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using namespace SST;
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using namespace SST::gem5;
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using namespace SST::MemHierarchy;
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ExtMaster::ExtMaster(gem5Component *g, Output &o, ::ExternalMaster& p,
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std::string &n) :
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Port(n, p), out(o), port(p), simPhase(CONSTRUCTION),
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gem5(g), name(n)
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{
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Params _p; // will be ignored
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nic = dynamic_cast<MemNIC*>(gem5->loadModuleWithComponent("memHierarchy.memNIC", g, _p));
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MemNIC::ComponentInfo ci;
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ci.num_vcs = 1;
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ci.link_port = "network";
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ci.link_bandwidth = "16GB/s";
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ci.link_inbuf_size = "1KB";
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ci.link_outbuf_size = "1KB";
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ci.network_addr = 0; // hard coded at the moment
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ci.type = MemNIC::TypeDirectoryCtrl;
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nic->moduleInit(ci, new Event::Handler<ExtMaster>
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(this, &ExtMaster::handleEvent));
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}
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void
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ExtMaster::init(unsigned phase)
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{
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simPhase = INIT;
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if (phase == 0) {
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assert(nic);
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for (auto range : getAddrRanges()) {
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MemNIC::ComponentTypeInfo ti;
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ti.rangeStart = range.start();
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ti.rangeEnd = range.end();
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ti.interleaveSize = 0;
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ti.interleaveStep = 0;
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nic->addTypeInfo(ti);
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ranges.insert(range);
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}
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}
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nic->init(phase);
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}
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void
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ExtMaster::setup(void)
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{
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nic->setup();
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simPhase = RUN;
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}
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void
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ExtMaster::finish(void)
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{
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nic->finish();
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}
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void
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ExtMaster::clock(void)
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{
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nic->clock();
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}
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void
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ExtMaster::handleEvent(SST::Event* event)
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{
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if (simPhase == CONSTRUCTION) {
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out.fatal(CALL_INFO, 1, "received Event during Construction phase\n");
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}
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MemEvent *ev = dynamic_cast<MemEvent*>(event);
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if (!ev) {
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out.fatal(CALL_INFO, 1, "Can't handle non-MemEvent Event's\n");
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}
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Command cmdI = ev->getCmd(); // command in - SST
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MemCmd::Command cmdO; // command out - gem5
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bool data = false;
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switch (cmdI) {
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case GetS: cmdO = MemCmd::ReadReq; break;
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case GetX: cmdO = MemCmd::WriteReq; data = true; break;
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case GetSEx:
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case PutS:
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case PutM:
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case PutE:
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case PutX:
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case PutXE:
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case Inv:
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case FetchInv:
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case FetchInvX:
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case NACK:
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case NULLCMD:
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case GetSResp:
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case GetXResp:
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case FetchResp:
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case FetchXResp:
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out.fatal(CALL_INFO, 1, "Don't know how to convert "
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"SST command %s to gem5\n",
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CommandString[cmdI]);
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}
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Request::FlagsType flags = 0;
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if (ev->queryFlag(MemEvent::F_LOCKED))
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flags |= Request::LOCKED_RMW;
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if (ev->queryFlag(MemEvent::F_NONCACHEABLE))
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flags |= Request::UNCACHEABLE;
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if (ev->isLoadLink()) {
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assert(cmdI == GetS);
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cmdO = MemCmd::LoadLockedReq;
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} else if (ev->isStoreConditional()) {
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assert(cmdI == GetX);
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cmdO = MemCmd::StoreCondReq;
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}
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auto req = new Request(ev->getAddr(), ev->getSize(), flags, 0);
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req->setThreadContext(ev->getGroupId(), 0);
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auto pkt = new Packet(req, cmdO);
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pkt->allocate();
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if (data) {
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pkt->setData(ev->getPayload().data());
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}
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pkt->pushSenderState(new SenderState(ev));
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if (blocked() || !sendTimingReq(pkt))
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sendQ.push_back(pkt);
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}
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bool
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ExtMaster::recvTimingResp(PacketPtr pkt) {
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if (simPhase == INIT) {
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out.fatal(CALL_INFO, 1, "not prepared to handle INIT-phase traffic\n");
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}
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// get original SST packet from gem5 SenderState
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auto senderState = dynamic_cast<SenderState*>(pkt->popSenderState());
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if (!senderState)
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out.fatal(CALL_INFO, 1, "gem5 senderState corrupt\n");
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// make (new) response packet, discard (old) original request
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MemEvent* ev = senderState->event;
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delete senderState;
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MemEvent* resp = ev->makeResponse();
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delete ev;
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// copy the payload and then destroy gem5 packet
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resp->setPayload(pkt->getSize(), pkt->getPtr<uint8_t>());
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delete pkt->req;
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delete pkt;
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nic->send(resp);
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return true;
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}
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void
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ExtMaster::recvReqRetry() {
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while (blocked() && sendTimingReq(sendQ.front())) {
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sendQ.pop_front();
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}
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}
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void
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ExtMaster::recvRangeChange() {
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for (auto range : getAddrRanges()) {
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if (ranges.find(range) == ranges.end()) { // i.e. if not found,
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MemNIC::ComponentTypeInfo ti; // indicating a new range.
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ti.rangeStart = range.start();
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ti.rangeEnd = range.end();
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ti.interleaveSize = 0;
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ti.interleaveStep = 0;
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nic->addTypeInfo(ti);
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ranges.insert(range);
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}
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}
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}
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