da6c1f5b09
src/arch/sparc/interrupts.hh:
add in thread_context.hh to get access to tc.
get rid of stubs that don't make sense right now.
implement checking and get softint interrupts
src/arch/sparc/miscregfile.cc:
softint should be OR-ed on a write.
src/arch/sparc/miscregfile.hh:
add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs.
src/arch/sparc/ua2005.cc:
implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write.
--HG--
extra : convert_revision : d12d1147b508121075ee9be4599693554d4b9eae
318 lines
9.9 KiB
C++
318 lines
9.9 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Ali Saidi
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*/
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#ifndef __ARCH_SPARC_MISCREGFILE_HH__
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#define __ARCH_SPARC_MISCREGFILE_HH__
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#include "arch/sparc/faults.hh"
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#include "arch/sparc/isa_traits.hh"
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#include "arch/sparc/types.hh"
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#include "cpu/cpuevent.hh"
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#include <string>
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namespace SparcISA
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{
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//These functions map register indices to names
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std::string getMiscRegName(RegIndex);
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enum MiscRegIndex
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{
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/** Ancillary State Registers */
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MISCREG_Y, /* 0 */
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MISCREG_CCR,
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MISCREG_ASI,
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MISCREG_TICK,
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MISCREG_FPRS,
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MISCREG_PCR,
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MISCREG_PIC,
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MISCREG_GSR,
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MISCREG_SOFTINT_SET,
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MISCREG_SOFTINT_CLR,
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MISCREG_SOFTINT, /* 10 */
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MISCREG_TICK_CMPR,
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MISCREG_STICK,
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MISCREG_STICK_CMPR,
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/** Privilged Registers */
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MISCREG_TPC,
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MISCREG_TNPC,
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MISCREG_TSTATE,
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MISCREG_TT,
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MISCREG_PRIVTICK,
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MISCREG_TBA,
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MISCREG_PSTATE, /* 20 */
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MISCREG_TL,
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MISCREG_PIL,
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MISCREG_CWP,
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MISCREG_CANSAVE,
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MISCREG_CANRESTORE,
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MISCREG_CLEANWIN,
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MISCREG_OTHERWIN,
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MISCREG_WSTATE,
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MISCREG_GL,
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/** Hyper privileged registers */
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MISCREG_HPSTATE, /* 30 */
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MISCREG_HTSTATE,
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MISCREG_HINTP,
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MISCREG_HTBA,
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MISCREG_HVER,
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MISCREG_STRAND_STS_REG,
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MISCREG_HSTICK_CMPR,
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/** Floating Point Status Register */
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MISCREG_FSR,
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/** MMU Internal Registers */
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MISCREG_MMU_P_CONTEXT,
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MISCREG_MMU_S_CONTEXT, /* 40 */
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MISCREG_MMU_PART_ID,
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MISCREG_MMU_LSU_CTRL,
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MISCREG_MMU_ITLB_C0_TSB_PS0,
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MISCREG_MMU_ITLB_C0_TSB_PS1,
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MISCREG_MMU_ITLB_C0_CONFIG,
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MISCREG_MMU_ITLB_CX_TSB_PS0,
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MISCREG_MMU_ITLB_CX_TSB_PS1,
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MISCREG_MMU_ITLB_CX_CONFIG,
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MISCREG_MMU_ITLB_SFSR,
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MISCREG_MMU_ITLB_TAG_ACCESS, /* 50 */
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MISCREG_MMU_DTLB_C0_TSB_PS0,
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MISCREG_MMU_DTLB_C0_TSB_PS1,
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MISCREG_MMU_DTLB_C0_CONFIG,
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MISCREG_MMU_DTLB_CX_TSB_PS0,
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MISCREG_MMU_DTLB_CX_TSB_PS1,
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MISCREG_MMU_DTLB_CX_CONFIG,
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MISCREG_MMU_DTLB_SFSR,
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MISCREG_MMU_DTLB_SFAR,
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MISCREG_MMU_DTLB_TAG_ACCESS,
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/** Scratchpad regiscers **/
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MISCREG_SCRATCHPAD_R0, /* 60 */
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MISCREG_SCRATCHPAD_R1,
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MISCREG_SCRATCHPAD_R2,
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MISCREG_SCRATCHPAD_R3,
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MISCREG_SCRATCHPAD_R4,
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MISCREG_SCRATCHPAD_R5,
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MISCREG_SCRATCHPAD_R6,
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MISCREG_SCRATCHPAD_R7,
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/* CPU Queue Registers */
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MISCREG_QUEUE_CPU_MONDO_HEAD,
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MISCREG_QUEUE_CPU_MONDO_TAIL,
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MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */
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MISCREG_QUEUE_DEV_MONDO_TAIL,
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MISCREG_QUEUE_RES_ERROR_HEAD,
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MISCREG_QUEUE_RES_ERROR_TAIL,
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MISCREG_QUEUE_NRES_ERROR_HEAD,
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MISCREG_QUEUE_NRES_ERROR_TAIL,
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MISCREG_NUMMISCREGS
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};
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enum HPStateFields {
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id = 0x800, // this impl. dependent (id) field must always be '1' for T1000
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ibe = 0x400,
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red = 0x20,
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hpriv = 0x4,
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tlz = 0x1
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};
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enum PStateFields {
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cle = 0x200,
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tle = 0x100,
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mm = 0xC0,
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pef = 0x10,
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am = 0x8,
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priv = 0x4,
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ie = 0x2
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};
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const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
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const int NumMiscRegs = MISCREG_NUMMISCREGS;
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// The control registers, broken out into fields
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class MiscRegFile
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{
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private:
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/* ASR Registers */
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uint64_t y; // Y (used in obsolete multiplication)
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uint8_t ccr; // Condition Code Register
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uint8_t asi; // Address Space Identifier
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uint64_t tick; // Hardware clock-tick counter
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uint8_t fprs; // Floating-Point Register State
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uint64_t gsr; // General Status Register
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uint64_t softint;
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uint64_t tick_cmpr; // Hardware tick compare registers
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uint64_t stick; // Hardware clock-tick counter
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uint64_t stick_cmpr; // Hardware tick compare registers
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/* Privileged Registers */
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uint64_t tpc[MaxTL]; // Trap Program Counter (value from
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// previous trap level)
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uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
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// previous trap level)
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uint64_t tstate[MaxTL]; // Trap State
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uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
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// on the previous level)
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uint64_t tba; // Trap Base Address
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uint16_t pstate; // Process State Register
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uint8_t tl; // Trap Level
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uint8_t pil; // Process Interrupt Register
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uint8_t cwp; // Current Window Pointer
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uint8_t cansave; // Savable windows
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uint8_t canrestore; // Restorable windows
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uint8_t cleanwin; // Clean windows
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uint8_t otherwin; // Other windows
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uint8_t wstate; // Window State
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uint8_t gl; // Global level register
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/** Hyperprivileged Registers */
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uint64_t hpstate; // Hyperprivileged State Register
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uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
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uint64_t hintp;
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uint64_t htba; // Hyperprivileged Trap Base Address register
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uint64_t hstick_cmpr; // Hardware tick compare registers
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uint64_t strandStatusReg;// Per strand status register
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/** Floating point misc registers. */
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uint64_t fsr; // Floating-Point State Register
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/** MMU Internal Registers */
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uint16_t priContext;
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uint16_t secContext;
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uint16_t partId;
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uint64_t lsuCtrlReg;
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uint64_t iTlbC0TsbPs0;
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uint64_t iTlbC0TsbPs1;
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uint64_t iTlbC0Config;
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uint64_t iTlbCXTsbPs0;
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uint64_t iTlbCXTsbPs1;
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uint64_t iTlbCXConfig;
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uint64_t iTlbSfsr;
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uint64_t iTlbTagAccess;
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uint64_t dTlbC0TsbPs0;
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uint64_t dTlbC0TsbPs1;
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uint64_t dTlbC0Config;
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uint64_t dTlbCXTsbPs0;
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uint64_t dTlbCXTsbPs1;
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uint64_t dTlbCXConfig;
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uint64_t dTlbSfsr;
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uint64_t dTlbSfar;
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uint64_t dTlbTagAccess;
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uint64_t scratchPad[8];
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uint64_t cpu_mondo_head;
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uint64_t cpu_mondo_tail;
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uint64_t dev_mondo_head;
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uint64_t dev_mondo_tail;
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uint64_t res_error_head;
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uint64_t res_error_tail;
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uint64_t nres_error_head;
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uint64_t nres_error_tail;
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// These need to check the int_dis field and if 0 then
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// set appropriate bit in softint and checkinterrutps on the cpu
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#if FULL_SYSTEM
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void setFSRegWithEffect(int miscReg, const MiscReg &val,
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ThreadContext *tc);
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MiscReg readFSRegWithEffect(int miscReg, ThreadContext * tc);
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/** Process a tick compare event and generate an interrupt on the cpu if
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* appropriate. */
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void processTickCompare(ThreadContext *tc);
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void processSTickCompare(ThreadContext *tc);
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void processHSTickCompare(ThreadContext *tc);
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typedef CpuEventWrapper<MiscRegFile,
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&MiscRegFile::processTickCompare> TickCompareEvent;
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TickCompareEvent *tickCompare;
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typedef CpuEventWrapper<MiscRegFile,
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&MiscRegFile::processSTickCompare> STickCompareEvent;
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STickCompareEvent *sTickCompare;
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typedef CpuEventWrapper<MiscRegFile,
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&MiscRegFile::processHSTickCompare> HSTickCompareEvent;
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HSTickCompareEvent *hSTickCompare;
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#endif
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public:
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void clear();
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MiscRegFile()
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{
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clear();
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}
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MiscReg readReg(int miscReg);
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MiscReg readRegWithEffect(int miscReg, ThreadContext *tc);
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void setReg(int miscReg, const MiscReg &val);
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void setRegWithEffect(int miscReg,
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const MiscReg &val, ThreadContext * tc);
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int getInstAsid()
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{
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return priContext | (uint32_t)partId << 13;
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}
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int getDataAsid()
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{
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return priContext | (uint32_t)partId << 13;
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}
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void serialize(std::ostream & os);
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void unserialize(Checkpoint * cp, const std::string & section);
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void copyMiscRegs(ThreadContext * tc);
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protected:
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bool isHyperPriv() { return (hpstate & (1 << 2)); }
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bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
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bool isNonPriv() { return !isPriv(); }
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};
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}
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#endif
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