cb9e208a4c
This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
860 lines
98 KiB
Plaintext
860 lines
98 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.026786 # Number of seconds simulated
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sim_ticks 26785824500 # Number of ticks simulated
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final_tick 26785824500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 121944 # Simulator instruction rate (inst/s)
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host_op_rate 122819 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 36056613 # Simulator tick rate (ticks/s)
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host_mem_usage 374016 # Number of bytes of host memory used
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host_seconds 742.88 # Real time elapsed on the host
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sim_insts 90589798 # Number of instructions simulated
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sim_ops 91240351 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 947840 # Number of bytes read from this memory
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system.physmem.bytes_read::total 992832 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 14810 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15513 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1679694 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 35385881 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 37065575 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1679694 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1679694 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1679694 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 35385881 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 37065575 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15513 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 15516 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 992832 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 992832 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 996 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 960 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 997 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 1012 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 996 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 1013 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 925 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 882 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 885 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 951 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 992 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 1001 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 966 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 968 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 968 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 1001 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 26785652500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 15513 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 0 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 10163 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 5065 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 255 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.totQLat 55611750 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 315006750 # Sum of mem lat for all requests
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system.physmem.totBusLat 77565000 # Total cycles spent in databus access
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system.physmem.totBankLat 181830000 # Total cycles spent in bank access
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system.physmem.avgQLat 3584.85 # Average queueing delay per request
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system.physmem.avgBankLat 11721.14 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 20305.99 # Average memory access latency
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system.physmem.avgRdBW 37.07 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 37.07 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 0.29 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.01 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 14781 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 95.28 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 1726658.45 # Average gap between requests
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system.cpu.branchPred.lookups 26682480 # Number of BP lookups
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system.cpu.branchPred.condPredicted 22002618 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 841998 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 11368270 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 11282813 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 99.248285 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 69658 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 194 # Number of incorrect RAS predictions.
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 442 # Number of system calls
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system.cpu.numCycles 53571650 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 14170612 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 127882618 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 26682480 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 11352471 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 24034762 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 4762849 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 11235788 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 13843090 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 329835 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 53345786 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.413719 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.215837 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 29349323 55.02% 55.02% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 3389433 6.35% 61.37% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 2028287 3.80% 65.17% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 1555177 2.92% 68.09% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 1667492 3.13% 71.21% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 2918592 5.47% 76.69% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 1510888 2.83% 79.52% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 1090794 2.04% 81.56% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 9835800 18.44% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 53345786 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.498071 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.387132 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 16933018 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 9083258 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 22434897 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 998703 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 3895910 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 4442085 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 8696 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 126062223 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 42630 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 3895910 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 18712984 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 3548131 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 156179 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 21551652 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 5480930 # Number of cycles rename is unblocking
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|
system.cpu.rename.RenamedInsts 123149853 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 423091 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 4597179 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.FullRegisterEvents 1286 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 143608098 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 536423645 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 536418417 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 5228 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 36193912 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 4607 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 4605 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 12518412 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 29475899 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 5522776 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 2125822 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 1253238 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 118167784 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 8472 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 105151160 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 77497 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 26739027 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 65605268 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 254 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 53345786 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.971124 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.910487 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 15316861 28.71% 28.71% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 11639595 21.82% 50.53% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 8263506 15.49% 66.02% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 6760248 12.67% 78.69% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 4974624 9.33% 88.02% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 2955128 5.54% 93.56% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 2464546 4.62% 98.18% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 527827 0.99% 99.17% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 443451 0.83% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 53345786 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 44563 6.73% 6.73% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 27 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 340033 51.38% 58.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 277229 41.89% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 74420309 70.77% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 155 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 201 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 25602989 24.35% 95.13% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 5116524 4.87% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 105151160 # Type of FU issued
|
|
system.cpu.iq.rate 1.962814 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 661852 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.006294 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 264386671 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 144919691 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 102682625 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 784 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 1077 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 339 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 105812622 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 390 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 443741 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 6901933 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 6293 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 6180 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 777932 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 31373 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 3895910 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 928973 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 127070 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 118188976 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 309212 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 29475899 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 5522776 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 4584 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 66075 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 6911 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 6180 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 446439 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 445443 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 891882 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 104175676 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 25284542 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 975484 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 12720 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 30343976 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 21325145 # Number of branches executed
|
|
system.cpu.iew.exec_stores 5059434 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.944605 # Inst execution rate
|
|
system.cpu.iew.wb_sent 102960011 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 102682964 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 62233069 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 104282875 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.916741 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.596772 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 26939053 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 833398 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 49449876 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.845363 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.541608 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 19967148 40.38% 40.38% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 13135707 26.56% 66.94% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 4163389 8.42% 75.36% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 3434332 6.95% 82.31% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1535763 3.11% 85.41% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 744463 1.51% 86.92% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 942034 1.91% 88.82% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 246412 0.50% 89.32% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 5280628 10.68% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 49449876 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 90602407 # Number of instructions committed
|
|
system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 27318810 # Number of memory references committed
|
|
system.cpu.commit.loads 22573966 # Number of loads committed
|
|
system.cpu.commit.membars 3888 # Number of memory barriers committed
|
|
system.cpu.commit.branches 18732304 # Number of branches committed
|
|
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 72525674 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 56148 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 5280628 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 162355527 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 240299704 # The number of ROB writes
|
|
system.cpu.timesIdled 43654 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 225864 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 90589798 # Number of Instructions Simulated
|
|
system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.591365 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.591365 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.691003 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.691003 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 495535708 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 120542575 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 173 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 431 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 29089632 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
|
|
system.cpu.icache.replacements 3 # number of replacements
|
|
system.cpu.icache.tagsinuse 630.397373 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 13842106 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 728 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 19013.881868 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 630.397373 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.307811 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.307811 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 13842106 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 13842106 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 13842106 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 13842106 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 13842106 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 13842106 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 983 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 49432499 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 49432499 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 49432499 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 49432499 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 49432499 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 49432499 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 13843089 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 13843089 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 13843089 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 13843089 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 13843089 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 13843089 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50287.384537 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 50287.384537 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 50287.384537 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 50287.384537 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 50287.384537 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 50287.384537 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 55.777778 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 250 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 250 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 250 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 250 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 250 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 250 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 733 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 733 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 733 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 733 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37907999 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 37907999 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37907999 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 37907999 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37907999 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 37907999 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51716.233288 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51716.233288 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51716.233288 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 51716.233288 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51716.233288 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 51716.233288 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 10760.479556 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1831525 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 15496 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 118.193405 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 9911.805562 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 616.761334 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 231.912660 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.302484 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.018822 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.007077 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.328384 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 903743 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 903767 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 942900 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 942900 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 29045 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 29045 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 932788 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 932812 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 932788 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 932812 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 704 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 281 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 985 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 14539 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 14539 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 704 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 14820 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 15524 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 704 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 14820 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 15524 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 36918500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15609500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 52528000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 628655000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 628655000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 36918500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 644264500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 681183000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 36918500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 644264500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 681183000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 728 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 904024 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 904752 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 942900 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 942900 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 43584 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 43584 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 728 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 947608 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 948336 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 728 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 947608 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 948336 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967033 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000311 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.001089 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.600000 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.333586 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.333586 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967033 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015639 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.016370 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967033 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015639 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.016370 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52441.051136 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55549.822064 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 53327.918782 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43239.218653 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43239.218653 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52441.051136 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 43472.638327 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 43879.348106 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52441.051136 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 43472.638327 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 43879.348106 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 703 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 974 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14539 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 14539 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 703 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 14810 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 15513 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 703 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 14810 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 15513 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27943554 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11832709 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 39776263 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 30003 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 30003 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 448424221 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 448424221 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27943554 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 460256930 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 488200484 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27943554 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 460256930 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 488200484 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000300 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001077 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.333586 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.333586 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015629 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016358 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015629 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016358 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39749.009957 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43663.132841 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40838.052361 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30842.851709 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30842.851709 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39749.009957 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31077.442944 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31470.410881 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39749.009957 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31077.442944 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31470.410881 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 943512 # number of replacements
|
|
system.cpu.dcache.tagsinuse 3674.906425 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 28139228 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 947608 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 29.695009 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 7938358000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 3674.906425 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.897194 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.897194 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 23594668 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 23594668 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 4536751 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 4536751 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3908 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 3908 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 28131419 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 28131419 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 28131419 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 28131419 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1172935 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1172935 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 198230 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 198230 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1371165 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1371165 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1371165 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1371165 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 13884681000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 13884681000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5602018407 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 5602018407 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 247000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 247000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 19486699407 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 19486699407 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 19486699407 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 19486699407 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 24767603 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 24767603 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3914 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 3914 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 29502584 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 29502584 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 29502584 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 29502584 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047358 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.047358 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041865 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.041865 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001533 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001533 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.046476 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.046476 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.046476 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.046476 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11837.553658 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 11837.553658 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28260.194759 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 28260.194759 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 41166.666667 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 41166.666667 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14211.782978 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 14211.782978 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14211.782978 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 14211.782978 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 152466 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 23833 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.397264 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 942900 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 942900 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 268897 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 268897 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154655 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 154655 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 423552 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 423552 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 423552 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 423552 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904038 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 904038 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43575 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 43575 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 947613 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 947613 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 947613 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 947613 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9990153500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9990153500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 984037459 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 984037459 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10974190959 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 10974190959 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10974190959 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 10974190959 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036501 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036501 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009203 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009203 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032120 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.032120 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032120 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.032120 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.590241 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.590241 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22582.615238 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22582.615238 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11580.878438 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11580.878438 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11580.878438 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11580.878438 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|