48e6ed48e0
dev/etherpkt.hh:
add some stuff for support of the NS ethernet device.
--HG--
extra : convert_revision : 51f6508463b6394055e3428a42b7de490a9ae6c1
404 lines
11 KiB
C++
404 lines
11 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* Device module for modelling the National Semiconductor
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* DP83820 ethernet controller
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*/
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#ifndef __NS_GIGE_HH__
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#define __NS_GIGE_HH__
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#include "dev/dma.hh"
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#include "dev/etherint.hh"
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#include "dev/etherpkt.hh"
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#include "sim/eventq.hh"
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#include "dev/ns_gige_reg.h"
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#include "base/statistics.hh"
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#include "dev/pcidev.hh"
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#include "dev/tsunami.hh"
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#include "dev/pciconfigall.hh"
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/** defined by the NS83820 data sheet */
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#define MAX_TX_FIFO_SIZE 8192
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#define MAX_RX_FIFO_SIZE 32768
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/** length of ethernet address in bytes */
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#define EADDR_LEN 6
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/** Transmit State Machine states */
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enum tx_state { txIdle, txDescRefr, txDescRead, txFifoBlock, txFragRead,
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txDescWrite };
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/** Receive State Machine States */
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enum rx_state { rxIdle, rxDescRefr, rxDescRead, rxFifoBlock, rxFragWrite,
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rxDescWrite, rxAdvance };
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/**
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* Ethernet device registers
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*/
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struct dp_regs {
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uint32_t command;
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uint32_t config;
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uint32_t mear;
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uint32_t ptscr;
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uint32_t isr;
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uint32_t imr;
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uint32_t ier;
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uint32_t ihr;
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uint32_t txdp;
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uint32_t txdp_hi;
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uint32_t txcfg;
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uint32_t gpior;
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uint32_t rxdp;
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uint32_t rxdp_hi;
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uint32_t rxcfg;
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uint32_t pqcr;
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uint32_t wcsr;
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uint32_t pcr;
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uint32_t rfcr;
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uint32_t rfdr;
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uint32_t srr;
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uint32_t mibc;
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uint32_t vrcr;
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uint32_t vtcr;
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uint32_t vdr;
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uint32_t ccsr;
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uint32_t tbicr;
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uint32_t tbisr;
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uint32_t tanar;
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uint32_t tanlpar;
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uint32_t taner;
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uint32_t tesr;
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/** for perfect match memory. the linux driver doesn't use any other ROM */
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uint8_t perfectMatch[EADDR_LEN];
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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/** an enum indicating direction, transmit or receive, used as a param for
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some fns */
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enum dir_t { tx, rx };
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class DmaEngine;
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class IntrControl;
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class EtherDevInt;
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class PhysicalMemory;
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/**
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* NS DP82830 Ethernet device model
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*/
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class EtherDev : public PciDev, public DmaHolder
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{
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private:
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/** pointer to the chipset */
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Tsunami *tsunami;
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protected:
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Addr addr;
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Addr mask;
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/** device register file */
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dp_regs regs;
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/*** BASIC STRUCTURES FOR TX/RX ***/
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/* Data FIFOs */
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typedef std::deque<PacketPtr> pktbuf_t;
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typedef pktbuf_t::iterator pktiter_t;
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pktbuf_t txFifo;
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pktbuf_t rxFifo;
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/** for the tx side, to track addrs to write updated cmdsts to */
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typedef std::deque<uint32_t> txdpbuf_t; /* ASSUME32 */
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txdpbuf_t descAddrFifo;
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/** various helper vars */
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uint32_t txPacketLen;
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uint8_t *txPacketBufPtr;
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uint8_t *rxPacketBufPtr;
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uint8_t *rxDescBufPtr;
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uint32_t fragLen;
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uint32_t rxCopied;
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/** DescCaches */
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ns_desc txDescCache;
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ns_desc rxDescCache;
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/* tx State Machine */
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tx_state txState;
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/** Current Transmit Descriptor Done */
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bool CTDD;
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uint32_t txFifoCnt; /* amt of data in the txDataFifo in bytes (logical) */
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uint32_t txFifoAvail; /* current amt of free space in txDataFifo in byes */
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bool txHalt;
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bool txPacketFlag; /* when set, indicates not working on a new packet */
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Addr txFragPtr; /* ptr to the next byte in the current fragment */
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uint32_t txDescCnt; /* count of bytes remaining in the current descriptor */
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/** rx State Machine */
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rx_state rxState;
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bool CRDD; /* Current Receive Descriptor Done */
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uint32_t rxPktBytes; /* num of bytes in the current packet being drained
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from rxDataFifo */
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uint32_t rxFifoCnt; /* number of bytes in the rxFifo */
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bool rxHalt;
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bool rxPacketFlag; /* when set, indicates not working on a new packet */
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Addr rxFragPtr; /* ptr to the next byte in current fragment */
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uint32_t rxDescCnt; /* count of bytes remaining in the current descriptor */
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bool extstsEnable;
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uint32_t maxTxBurst;
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uint32_t maxRxBurst;
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PhysicalMemory *physmem;
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protected:
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/**
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* Receive dma for descriptors done callback
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*/
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class RxDescDone : public DmaCallback
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{
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public:
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EtherDev *ethernet;
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public:
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RxDescDone(EtherDev *e);
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std::string name() const;
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virtual void process();
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};
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/**
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* Receive dma done callback
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*/
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class RxDone : public DmaCallback
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{
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public:
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EtherDev *ethernet;
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public:
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RxDone(EtherDev *e);
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std::string name() const;
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virtual void process();
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};
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/**
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* Transmit dma for descriptors done callback
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*/
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class TxDescDone : public DmaCallback
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{
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public:
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EtherDev *ethernet;
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public:
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TxDescDone(EtherDev *e);
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std::string name() const;
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virtual void process();
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};
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/*
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* Transmit dma done callback
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*/
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class TxDone : public DmaCallback
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{
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public:
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EtherDev *ethernet;
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PacketPtr packet;
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public:
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TxDone(EtherDev *e);
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std::string name() const;
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virtual void process();
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};
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friend class TxDescDone;
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friend class TxDone;
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friend class RxDescDone;
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friend class RxDone;
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RxDescDone rxDescDoneCB;
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RxDone rxDoneCB;
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TxDescDone txDescDoneCB;
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TxDone txDoneCB;
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DmaEngine *dma;
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DmaRequest readRequest;
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DmaRequest writeRequest;
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DmaRequest readDescRequest;
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DmaRequest writeDescRequest;
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PacketPtr rxPacket;
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DmaPhys readPhys;
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DmaPhys writePhys;
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DmaPhys readDescPhys;
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DmaPhys writeDescPhys;
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EtherDevInt *interface;
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protected:
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IntrControl *intctrl;
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Tick txDelay;
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Tick rxDelay;
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void txReset();
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void rxReset();
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void regsReset() {
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memset(®s, 0, sizeof(regs));
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regs.mear = 0x12;
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regs.isr = 0x00608000;
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regs.txcfg = 0x120;
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regs.rxcfg = 0x4;
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regs.srr = 0x0103;
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regs.mibc = 0x2;
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regs.vdr = 0x81;
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regs.tesr = 0xc000;
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}
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void txKick();
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void rxKick();
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/*
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* Retransmit event
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*/
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class TxEvent : public Event
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{
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protected:
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EtherDev *dev;
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public:
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TxEvent(EtherDev *_dev)
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: Event(&mainEventQueue), dev(_dev) {}
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void process() { dev->transmit(); }
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virtual const char *description() { return "retransmit"; }
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};
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friend class TxEvent;
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TxEvent txEvent;
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void transmit();
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void txDescDone();
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void rxDescDone();
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void txDone(PacketPtr packet);
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void rxDone();
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void txDump() const;
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void rxDump() const;
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void devIntrPost(uint32_t interrupts);
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void devIntrClear(uint32_t interrupts);
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void devIntrChangeMask();
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bool cpuPendingIntr;
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void cpuIntrPost();
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void cpuIntrClear();
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bool rxFilterEnable;
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bool rxFilter(PacketPtr packet);
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bool acceptBroadcast;
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bool acceptMulticast;
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bool acceptUnicast;
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bool acceptPerfect;
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bool acceptArp;
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bool udpChecksum(PacketPtr packet, bool gen);
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bool tcpChecksum(PacketPtr packet, bool gen);
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bool ipChecksum(PacketPtr packet, bool gen);
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uint16_t checksumCalc(uint16_t *pseudo, uint16_t *buf, uint32_t len);
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public:
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EtherDev(const std::string &name, DmaEngine *de, bool use_interface,
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IntrControl *i, MemoryController *mmu, PhysicalMemory *pmem,
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PCIConfigAll *cf, PciConfigData *cd, Tsunami *t, uint32_t bus,
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uint32_t dev, uint32_t func, bool rx_filter, const int eaddr[6],
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Tick tx_delay, Tick rx_delay, Addr addr, Addr mask);
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~EtherDev();
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virtual void WriteConfig(int offset, int size, uint32_t data);
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virtual void ReadConfig(int offset, int size, uint8_t *data);
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Fault read(MemReqPtr req, uint8_t *data);
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Fault write(MemReqPtr req, const uint8_t *data);
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bool cpuIntrPending() const;
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void cpuIntrAck() { cpuIntrClear(); }
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bool recvPacket(PacketPtr packet);
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void transferDone();
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void setInterface(EtherDevInt *i) { assert(!interface); interface = i; }
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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virtual DmaRequest *find_dmareq(uint32_t &id) {
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if (id == 0)
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return(&readRequest);
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else if (id == 1)
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return(&writeRequest);
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else
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return(NULL);
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}
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public:
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void regStats();
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private:
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Statistics::Scalar<> txBytes;
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Statistics::Scalar<> rxBytes;
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Statistics::Scalar<> txPackets;
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Statistics::Scalar<> rxPackets;
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Statistics::Formula txBandwidth;
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Statistics::Formula rxBandwidth;
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Statistics::Formula txPacketRate;
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Statistics::Formula rxPacketRate;
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void readOneDesc(dir_t dir, uint32_t len = sizeof(ns_desc));
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void readOneFrag();
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void writeOneFrag();
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};
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/*
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* Ethernet Interface for an Ethernet Device
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*/
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class EtherDevInt : public EtherInt
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{
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private:
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EtherDev *dev;
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public:
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EtherDevInt(const std::string &name, EtherDev *d)
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: EtherInt(name), dev(d) { dev->setInterface(this); }
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virtual bool recvPacket(PacketPtr &pkt) { return dev->recvPacket(pkt); }
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virtual void sendDone() { dev->transferDone(); }
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};
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#endif // __NS_GIGE_HH__
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