48b6636d01
Pass in a bool to indicate if the fault is from a store instead of having two different classes. The classes were also misleadingly named since loads are also processed by the DTB but should return ITB faults since they aren't stores. The TLB may be returning the wrong fault in this case, but I haven't looked at it closely.
394 lines
12 KiB
C++
394 lines
12 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Korey Sewell
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* Jaidev Patwardhan
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*/
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#include "arch/mips/faults.hh"
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#include "arch/mips/pra_constants.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "debug/MipsPRA.hh"
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#if !FULL_SYSTEM
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#include "mem/page_table.hh"
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#include "sim/process.hh"
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#endif
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namespace MipsISA
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{
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typedef MipsFaultBase::FaultVals FaultVals;
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template <> FaultVals MipsFault<MachineCheckFault>::vals =
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{ "Machine Check", 0x0401 };
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template <> FaultVals MipsFault<ResetFault>::vals =
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#if FULL_SYSTEM
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{ "Reset Fault", 0xBFC00000};
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#else
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{ "Reset Fault", 0x001};
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#endif
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template <> FaultVals MipsFault<AddressErrorFault>::vals =
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{ "Address Error", 0x0180 };
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template <> FaultVals MipsFault<SystemCallFault>::vals =
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{ "Syscall", 0x0180 };
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template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals =
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{ "Coprocessor Unusable Fault", 0x180 };
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template <> FaultVals MipsFault<ReservedInstructionFault>::vals =
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{ "Reserved Instruction Fault", 0x0180 };
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template <> FaultVals MipsFault<ThreadFault>::vals =
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{ "Thread Fault", 0x00F1 };
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template <> FaultVals MipsFault<IntegerOverflowFault>::vals =
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{ "Integer Overflow Exception", 0x180 };
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template <> FaultVals MipsFault<InterruptFault>::vals =
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{ "interrupt", 0x0180 };
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template <> FaultVals MipsFault<TrapFault>::vals =
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{ "Trap", 0x0180 };
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template <> FaultVals MipsFault<BreakpointFault>::vals =
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{ "Breakpoint", 0x0180 };
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template <> FaultVals MipsFault<TlbInvalidFault>::vals =
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{ "Invalid TLB Entry Exception", 0x0180 };
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template <> FaultVals MipsFault<TlbRefillFault>::vals =
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{ "TLB Refill Exception", 0x0180 };
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template <> FaultVals MipsFault<TLBModifiedFault>::vals =
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{ "TLB Modified Exception", 0x0180 };
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template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
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{ "DSP Disabled Fault", 0x001a };
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#if FULL_SYSTEM
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void
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MipsFaultBase::setHandlerPC(Addr HandlerBase, ThreadContext *tc)
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{
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tc->setPC(HandlerBase);
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tc->setNextPC(HandlerBase + sizeof(MachInst));
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tc->setNextNPC(HandlerBase + 2 * sizeof(MachInst));
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}
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void
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MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
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{
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// modify SRS Ctl - Save CSS, put ESS into CSS
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StatusReg status = tc->readMiscReg(MISCREG_STATUS);
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if (status.exl != 1 && status.bev != 1) {
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// SRS Ctl is modified only if Status_EXL and Status_BEV are not set
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SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL);
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srsCtl.pss = srsCtl.css;
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srsCtl.css = srsCtl.ess;
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tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl);
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}
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// set EXL bit (don't care if it is already set!)
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status.exl = 1;
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tc->setMiscRegNoEffect(MISCREG_STATUS, status);
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// write EPC
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// CHECK ME or FIXME or FIX ME or POSSIBLE HACK
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// Check to see if the exception occurred in the branch delay slot
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DPRINTF(MipsPRA, "PC: %x, NextPC: %x, NNPC: %x\n",
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tc->readPC(), tc->readNextPC(), tc->readNextNPC());
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int bd = 0;
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if (tc->readPC() + sizeof(MachInst) != tc->readNextPC()) {
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tc->setMiscRegNoEffect(MISCREG_EPC, tc->readPC() - sizeof(MachInst));
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// In the branch delay slot? set CAUSE_31
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bd = 1;
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} else {
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tc->setMiscRegNoEffect(MISCREG_EPC, tc->readPC());
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// In the branch delay slot? reset CAUSE_31
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bd = 0;
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}
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// Set Cause_EXCCODE field
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CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
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cause.excCode = excCode;
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cause.bd = bd;
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cause.ce = 0;
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tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
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}
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void
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IntegerOverflowFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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setExceptionState(tc, 0xC);
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// Set new PC
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Addr HandlerBase;
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StatusReg status = tc->readMiscReg(MISCREG_STATUS);
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// Here, the handler is dependent on BEV, which is not modified by
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// setExceptionState()
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if (!status.bev) {
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// See MIPS ARM Vol 3, Revision 2, Page 38
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HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
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} else {
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HandlerBase = 0xBFC00200;
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}
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setHandlerPC(HandlerBase, tc);
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}
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void
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TrapFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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setExceptionState(tc, 0xD);
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// Set new PC
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Addr HandlerBase;
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// Offset 0x180 - General Exception Vector
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HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
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setHandlerPC(HandlerBase, tc);
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}
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void
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BreakpointFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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setExceptionState(tc, 0x9);
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// Set new PC
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Addr HandlerBase;
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// Offset 0x180 - General Exception Vector
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HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
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setHandlerPC(HandlerBase, tc);
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}
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void
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TlbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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setExceptionState(tc, store ? 0x3 : 0x2);
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tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
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EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
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entryHi.asid = entryHiAsid;
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entryHi.vpn2 = entryHiVPN2;
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entryHi.vpn2x = entryHiVPN2X;
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tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
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ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
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context.badVPN2 = contextBadVPN2;
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tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
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// Set new PC
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Addr HandlerBase;
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// Offset 0x180 - General Exception Vector
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HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
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setHandlerPC(HandlerBase, tc);
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}
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void
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AddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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setExceptionState(tc, store ? 0x5 : 0x4);
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tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
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// Set new PC
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Addr HandlerBase;
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// Offset 0x180 - General Exception Vector
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HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
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setHandlerPC(HandlerBase, tc);
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}
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void
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TlbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR);
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setExceptionState(tc, store ? 0x3 : 0x2);
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Addr HandlerBase;
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tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
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EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
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entryHi.asid = entryHiAsid;
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entryHi.vpn2 = entryHiVPN2;
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entryHi.vpn2x = entryHiVPN2X;
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tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
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ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
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context.badVPN2 = contextBadVPN2;
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tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
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StatusReg status = tc->readMiscReg(MISCREG_STATUS);
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// Since handler depends on EXL bit, must check EXL bit before setting it!!
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// See MIPS ARM Vol 3, Revision 2, Page 38
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if (status.exl == 1) {
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// Offset 0x180 - General Exception Vector
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HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
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} else {
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// Offset 0x000
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HandlerBase = tc->readMiscReg(MISCREG_EBASE);
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}
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setHandlerPC(HandlerBase, tc);
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}
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void
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TLBModifiedFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
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EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
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entryHi.asid = entryHiAsid;
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entryHi.vpn2 = entryHiVPN2;
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entryHi.vpn2x = entryHiVPN2X;
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tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
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ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
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context.badVPN2 = contextBadVPN2;
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tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
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// Set new PC
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Addr HandlerBase;
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// Offset 0x180 - General Exception Vector
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HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
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setExceptionState(tc, 0x1);
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setHandlerPC(HandlerBase, tc);
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}
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void
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SystemCallFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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setExceptionState(tc, 0x8);
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// Set new PC
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Addr HandlerBase;
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// Offset 0x180 - General Exception Vector
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HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
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setHandlerPC(HandlerBase, tc);
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}
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void
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InterruptFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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#if FULL_SYSTEM
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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setExceptionState(tc, 0x0A);
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Addr HandlerBase;
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CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
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if (cause.iv) {
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// Offset 200 for release 2
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HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(MISCREG_EBASE);
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} else {
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//Ofset at 180 for release 1
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HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE);
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}
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setHandlerPC(HandlerBase, tc);
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#endif
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}
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#endif // FULL_SYSTEM
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void
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ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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#if FULL_SYSTEM
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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/* All reset activity must be invoked from here */
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tc->setPC(vect());
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tc->setNextPC(vect() + sizeof(MachInst));
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tc->setNextNPC(vect() + sizeof(MachInst) + sizeof(MachInst));
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DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", tc->readPC());
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#endif
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// Set Coprocessor 1 (Floating Point) To Usable
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StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
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status.cu.cu1 = 1;
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tc->setMiscReg(MISCREG_STATUS, status);
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}
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void
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ReservedInstructionFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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#if FULL_SYSTEM
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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setExceptionState(tc, 0x0A);
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Addr HandlerBase;
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// Offset 0x180 - General Exception Vector
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HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE);
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setHandlerPC(HandlerBase, tc);
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#else
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panic("%s encountered.\n", name());
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#endif
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}
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void
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ThreadFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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panic("%s encountered.\n", name());
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}
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void
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DspStateDisabledFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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panic("%s encountered.\n", name());
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}
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void
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CoprocessorUnusableFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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#if FULL_SYSTEM
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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setExceptionState(tc, 0xb);
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// The ID of the coprocessor causing the exception is stored in
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// CoprocessorUnusableFault::coProcID
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CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
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cause.ce = coProcID;
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tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
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Addr HandlerBase;
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// Offset 0x180 - General Exception Vector
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HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
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setHandlerPC(HandlerBase, tc);
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#else
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warn("%s (CP%d) encountered.\n", name(), coProcID);
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#endif
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}
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} // namespace MipsISA
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