48281375ee
The Request::UNCACHEABLE flag currently has two different functions. The first, and obvious, function is to prevent the memory system from caching data in the request. The second function is to prevent reordering and speculation in CPU models. This changeset gives the order/speculation requirement a separate flag (Request::STRICT_ORDER). This flag prevents CPU models from doing the following optimizations: * Speculation: CPU models are not allowed to issue speculative loads. * Write combining: CPU models and caches are not allowed to merge writes to the same cache line. Note: The memory system may still reorder accesses unless the UNCACHEABLE flag is set. It is therefore expected that the STRICT_ORDER flag is combined with the UNCACHEABLE flag to prevent this behavior.
358 lines
8.7 KiB
C++
358 lines
8.7 KiB
C++
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* Copyright (c) 2007-2008 The Florida State University
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* Copyright (c) 2009 The University of Edinburgh
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Steve Reinhardt
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* Jaidev Patwardhan
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* Stephen Hines
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* Timothy M. Jones
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*/
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#include <string>
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#include <vector>
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#include "arch/power/faults.hh"
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#include "arch/power/pagetable.hh"
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#include "arch/power/tlb.hh"
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#include "arch/power/utility.hh"
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#include "base/inifile.hh"
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#include "base/str.hh"
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#include "base/trace.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Power.hh"
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#include "debug/TLB.hh"
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#include "mem/page_table.hh"
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#include "params/PowerTLB.hh"
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#include "sim/full_system.hh"
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#include "sim/process.hh"
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using namespace std;
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using namespace PowerISA;
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///////////////////////////////////////////////////////////////////////
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//
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// POWER TLB
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//
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#define MODE2MASK(X) (1 << (X))
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TLB::TLB(const Params *p)
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: BaseTLB(p), size(p->size), nlu(0)
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{
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table = new PowerISA::PTE[size];
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memset(table, 0, sizeof(PowerISA::PTE[size]));
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smallPages = 0;
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}
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TLB::~TLB()
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{
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if (table)
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delete [] table;
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}
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// look up an entry in the TLB
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PowerISA::PTE *
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TLB::lookup(Addr vpn, uint8_t asn) const
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{
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// assume not found...
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PowerISA::PTE *retval = NULL;
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PageTable::const_iterator i = lookupTable.find(vpn);
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if (i != lookupTable.end()) {
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while (i->first == vpn) {
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int index = i->second;
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PowerISA::PTE *pte = &table[index];
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Addr Mask = pte->Mask;
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Addr InvMask = ~Mask;
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Addr VPN = pte->VPN;
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if (((vpn & InvMask) == (VPN & InvMask))
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&& (pte->G || (asn == pte->asid))) {
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// We have a VPN + ASID Match
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retval = pte;
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break;
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}
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++i;
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}
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}
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DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
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retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
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return retval;
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}
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PowerISA::PTE*
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TLB::getEntry(unsigned Index) const
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{
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// Make sure that Index is valid
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assert(Index<size);
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return &table[Index];
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}
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int
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TLB::probeEntry(Addr vpn,uint8_t asn) const
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{
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// assume not found...
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int Ind = -1;
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PageTable::const_iterator i = lookupTable.find(vpn);
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if (i != lookupTable.end()) {
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while (i->first == vpn) {
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int index = i->second;
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PowerISA::PTE *pte = &table[index];
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Addr Mask = pte->Mask;
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Addr InvMask = ~Mask;
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Addr VPN = pte->VPN;
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if (((vpn & InvMask) == (VPN & InvMask))
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&& (pte->G || (asn == pte->asid))) {
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// We have a VPN + ASID Match
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Ind = index;
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break;
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}
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++i;
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}
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}
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DPRINTF(Power, "VPN: %x, asid: %d, Result of TLBP: %d\n", vpn, asn, Ind);
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return Ind;
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}
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inline Fault
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TLB::checkCacheability(RequestPtr &req)
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{
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Addr VAddrUncacheable = 0xA0000000;
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if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
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// mark request as uncacheable
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req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
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}
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return NoFault;
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}
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void
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TLB::insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages)
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{
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smallPages=_smallPages;
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if (Index > size){
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warn("Attempted to write at index (%d) beyond TLB size (%d)",
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Index, size);
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} else {
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// Update TLB
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if (table[Index].V0 || table[Index].V1) {
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// Previous entry is valid
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PageTable::iterator i = lookupTable.find(table[Index].VPN);
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lookupTable.erase(i);
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}
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table[Index]=pte;
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// Update fast lookup table
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lookupTable.insert(make_pair(table[Index].VPN, Index));
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}
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}
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// insert a new TLB entry
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void
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TLB::insert(Addr addr, PowerISA::PTE &pte)
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{
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fatal("TLB Insert not yet implemented\n");
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}
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void
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TLB::flushAll()
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{
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DPRINTF(TLB, "flushAll\n");
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memset(table, 0, sizeof(PowerISA::PTE[size]));
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lookupTable.clear();
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nlu = 0;
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}
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void
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TLB::serialize(ostream &os)
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{
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SERIALIZE_SCALAR(size);
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SERIALIZE_SCALAR(nlu);
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for (int i = 0; i < size; i++) {
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nameOut(os, csprintf("%s.PTE%d", name(), i));
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table[i].serialize(os);
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}
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}
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void
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TLB::unserialize(Checkpoint *cp, const string §ion)
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{
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UNSERIALIZE_SCALAR(size);
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UNSERIALIZE_SCALAR(nlu);
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for (int i = 0; i < size; i++) {
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table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
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if (table[i].V0 || table[i].V1) {
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lookupTable.insert(make_pair(table[i].VPN, i));
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}
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}
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}
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void
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TLB::regStats()
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{
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read_hits
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.name(name() + ".read_hits")
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.desc("DTB read hits")
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;
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read_misses
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.name(name() + ".read_misses")
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.desc("DTB read misses")
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;
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read_accesses
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.name(name() + ".read_accesses")
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.desc("DTB read accesses")
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;
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write_hits
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.name(name() + ".write_hits")
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.desc("DTB write hits")
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;
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write_misses
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.name(name() + ".write_misses")
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.desc("DTB write misses")
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;
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write_accesses
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.name(name() + ".write_accesses")
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.desc("DTB write accesses")
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;
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hits
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.name(name() + ".hits")
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.desc("DTB hits")
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;
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misses
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.name(name() + ".misses")
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.desc("DTB misses")
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;
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accesses
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.name(name() + ".accesses")
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.desc("DTB accesses")
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;
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hits = read_hits + write_hits;
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misses = read_misses + write_misses;
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accesses = read_accesses + write_accesses;
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}
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Fault
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TLB::translateInst(RequestPtr req, ThreadContext *tc)
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{
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// Instruction accesses must be word-aligned
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if (req->getVaddr() & 0x3) {
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DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
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req->getSize());
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return std::make_shared<AlignmentFault>();
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}
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Process * p = tc->getProcessPtr();
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Fault fault = p->pTable->translate(req);
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if (fault != NoFault)
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return fault;
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return NoFault;
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}
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Fault
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TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
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{
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Process * p = tc->getProcessPtr();
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Fault fault = p->pTable->translate(req);
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if (fault != NoFault)
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return fault;
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return NoFault;
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}
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Fault
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TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
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{
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if (FullSystem)
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fatal("translate atomic not yet implemented in full system mode.\n");
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if (mode == Execute)
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return translateInst(req, tc);
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else
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return translateData(req, tc, mode == Write);
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}
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void
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TLB::translateTiming(RequestPtr req, ThreadContext *tc,
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Translation *translation, Mode mode)
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{
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assert(translation);
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translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
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}
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Fault
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TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
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{
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panic("Not implemented\n");
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return NoFault;
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}
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Fault
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TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
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{
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return NoFault;
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}
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PowerISA::PTE &
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TLB::index(bool advance)
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{
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PowerISA::PTE *pte = &table[nlu];
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if (advance)
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nextnlu();
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return *pte;
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}
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PowerISA::TLB *
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PowerTLBParams::create()
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{
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return new PowerISA::TLB(this);
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}
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