cb9e208a4c
This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
1282 lines
149 KiB
Text
1282 lines
149 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.182958 # Number of seconds simulated
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sim_ticks 1182958259000 # Number of ticks simulated
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final_tick 1182958259000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 332432 # Simulator instruction rate (inst/s)
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host_op_rate 423606 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 6399087906 # Simulator tick rate (ticks/s)
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host_mem_usage 408760 # Number of bytes of host memory used
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host_seconds 184.86 # Real time elapsed on the host
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sim_insts 61454647 # Number of instructions simulated
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sim_ops 78309315 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 4709236 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 4815472 # Number of bytes read from this memory
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system.physmem.bytes_read::total 62146212 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4116096 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7143440 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 73654 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 75268 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 6654489 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 64314 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 821150 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 43876875 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 332539 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 3980898 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 273183 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 4070703 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 52534577 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 332539 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 273183 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 605722 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 3479494 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 14371 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 2544759 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 6038624 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 3479494 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 43876875 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 332539 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 3995269 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 273183 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 6615462 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 58573201 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 6654489 # Total number of read requests seen
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system.physmem.writeReqs 821150 # Total number of write requests seen
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system.physmem.cpureqs 235683 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 425887296 # Total number of bytes read from memory
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system.physmem.bytesWritten 52553600 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 62146212 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 7143440 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 112 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 11769 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 422283 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 415708 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 415257 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 415923 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 415836 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 415086 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 415138 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 415982 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 415774 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 415145 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 415183 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 415686 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 415664 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 415065 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 414968 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 415679 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 51312 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 51158 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 50892 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 51475 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 51354 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 50696 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 50735 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 51449 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 51887 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 51295 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 51778 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 51726 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 51254 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 51118 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 51796 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 1182953705000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 6825 # Categorize read packet sizes
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system.physmem.readPktSize::3 6488064 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 159600 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 756836 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 64314 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 571059 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 408588 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 415867 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 1537787 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 1165425 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1169620 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1140545 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 29607 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 27579 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 48460 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 69110 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 48185 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 5882 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 5724 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 5512 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 5352 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 75 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 35451 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 35680 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 35684 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 35689 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 35694 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 35695 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 35698 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 35700 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 35702 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 35702 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 35702 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 35702 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 35702 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 35702 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 35702 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 35702 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 35702 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 35702 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 35702 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 35702 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 35702 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 35702 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 35702 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 252 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 19 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.totQLat 147016739500 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 189339617000 # Sum of mem lat for all requests
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system.physmem.totBusLat 33271885000 # Total cycles spent in databus access
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system.physmem.totBankLat 9050992500 # Total cycles spent in bank access
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system.physmem.avgQLat 22093.24 # Average queueing delay per request
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system.physmem.avgBankLat 1360.16 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 28453.39 # Average memory access latency
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system.physmem.avgRdBW 360.02 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 44.43 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 52.53 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 3.16 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.16 # Average read queue length over time
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system.physmem.avgWrQLen 12.52 # Average write queue length over time
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system.physmem.readRowHits 6612346 # Number of row buffer hits during reads
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system.physmem.writeRowHits 800481 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 99.37 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 97.48 # Row buffer hit rate for writes
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system.physmem.avgGap 158241.15 # Average gap between requests
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system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
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system.l2c.replacements 69480 # number of replacements
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system.l2c.tagsinuse 53041.287373 # Cycle average of tags in use
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system.l2c.total_refs 1677464 # Total number of references to valid blocks.
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system.l2c.sampled_refs 134656 # Sample count of references to valid blocks.
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system.l2c.avg_refs 12.457403 # Average number of references to valid blocks.
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system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.l2c.occ_blocks::writebacks 40190.252096 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.dtb.walker 0.000406 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.itb.walker 0.001419 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.inst 3727.107062 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.data 4236.234020 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu1.dtb.walker 2.741995 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu1.inst 2823.629298 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu1.data 2061.321078 # Average occupied blocks per requestor
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system.l2c.occ_percent::writebacks 0.613255 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu0.inst 0.056871 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu0.data 0.064640 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu1.inst 0.043085 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu1.data 0.031453 # Average percentage of cache occupancy
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system.l2c.occ_percent::total 0.809346 # Average percentage of cache occupancy
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system.l2c.ReadReq_hits::cpu0.dtb.walker 3740 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu0.itb.walker 1661 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu0.inst 419713 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu0.data 206323 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu1.dtb.walker 5388 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu1.itb.walker 1856 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 464159 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 143887 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1246727 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 572264 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 572264 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 1120 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 606 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 1726 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 216 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 100 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 316 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 57066 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 52392 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 109458 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 3740 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 1661 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 419713 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 263389 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 5388 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 1856 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 464159 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 196279 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1356185 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 3740 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 1661 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 419713 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 263389 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 5388 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 1856 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 464159 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 196279 # number of overall hits
|
|
system.l2c.overall_hits::total 1356185 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 5733 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 7863 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 5044 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 3624 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 22271 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 4701 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 3596 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 8297 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 563 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 469 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 1032 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 67050 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 72720 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 139770 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 5733 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 74913 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 5044 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 76344 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 162041 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 5733 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 74913 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 5044 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 76344 # number of overall misses
|
|
system.l2c.overall_misses::total 162041 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 69000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 299840500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 416754500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 247500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 276698000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 223564500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 1217256500 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 12757497 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 11938999 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 24696496 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1598500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2408500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 4007000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 3004157980 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 3438233497 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 6442391477 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 299840500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 3420912480 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 247500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 276698000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 3661797997 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 7659647977 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 299840500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 3420912480 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 247500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 276698000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 3661797997 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 7659647977 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 3741 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 1663 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.inst 425446 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 214186 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 5392 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 1856 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 469203 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 147511 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 1268998 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 572264 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 572264 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 5821 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 4202 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 10023 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 779 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 569 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 1348 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 124116 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 125112 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 249228 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 3741 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 1663 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 425446 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 338302 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 5392 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 1856 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 469203 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 272623 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 1518226 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 3741 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 1663 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 425446 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 338302 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 5392 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 1856 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 469203 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 272623 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 1518226 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000267 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001203 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.013475 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.036711 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000742 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.010750 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.024568 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.017550 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.807593 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.855783 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.827796 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.722721 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.824253 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.765579 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.540220 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.581239 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.560812 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000267 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.001203 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.013475 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.221438 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000742 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.010750 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.280035 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.106730 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000267 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.001203 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.013475 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.221438 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000742 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.010750 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.280035 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.106730 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 69000 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 41250 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52300.802372 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.data 53001.971258 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 61875 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 54856.859635 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 61689.983444 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 54656.571326 # average ReadReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2713.783663 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3320.077586 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 2976.557310 # average UpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2839.253996 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5135.394456 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 3882.751938 # average SCUpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44804.742431 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47280.438628 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 46092.805874 # average ReadExReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 41250 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 52300.802372 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 45665.137960 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 54856.859635 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 47964.450343 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 47269.814288 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 41250 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 52300.802372 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 45665.137960 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 54856.859635 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 47964.450343 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 47269.814288 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 64314 # number of writebacks
|
|
system.l2c.writebacks::total 64314 # number of writebacks
|
|
system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
|
|
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.inst 5732 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.data 7863 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.inst 5044 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.data 3624 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::total 22270 # number of ReadReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 4701 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 3596 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 8297 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 563 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 469 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 1032 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 67050 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 72720 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 139770 # number of ReadExReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 5732 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 74913 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 5044 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 76344 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 162040 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 5732 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 74913 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 5044 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 76344 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 162040 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56251 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 57502 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 227938476 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 318715113 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 197504 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 213513533 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 178263373 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 938741752 # number of ReadReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 47096148 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 36051561 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 83147709 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5658050 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4702967 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 10361017 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2154770965 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2528315165 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 4683086130 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 57502 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 227938476 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 2473486078 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 197504 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 213513533 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 2706578538 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 5621827882 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56251 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 57502 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 227938476 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 2473486078 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 197504 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 213513533 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 2706578538 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 5621827882 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 209633632 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12454649323 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3082087 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154326885776 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 166994250818 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000448248 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8209486413 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 9209934661 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 209633632 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13455097571 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3082087 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162536372189 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 176204185479 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000267 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001203 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036711 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000742 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024568 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.017549 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.807593 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.855783 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.827796 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.722721 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.824253 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.765579 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540220 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.581239 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.560812 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000267 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001203 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.221438 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000742 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.280035 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.106730 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000267 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001203 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.221438 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000742 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.280035 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.106730 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39765.958828 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40533.525754 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42330.200833 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49189.672461 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 42152.750427 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10018.325463 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10025.461902 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10021.418465 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10049.822380 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.648188 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10039.745155 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32136.778001 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34767.810300 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 33505.660228 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39765.958828 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33018.115387 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42330.200833 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35452.406712 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 34694.074809 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39765.958828 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33018.115387 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42330.200833 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35452.406712 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 34694.074809 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 7073604 # DTB read hits
|
|
system.cpu0.dtb.read_misses 3763 # DTB read misses
|
|
system.cpu0.dtb.write_hits 5658971 # DTB write hits
|
|
system.cpu0.dtb.write_misses 806 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 7077367 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 5659777 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 12732575 # DTB hits
|
|
system.cpu0.dtb.misses 4569 # DTB misses
|
|
system.cpu0.dtb.accesses 12737144 # DTB accesses
|
|
system.cpu0.itb.inst_hits 29573368 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 2205 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 29575573 # ITB inst accesses
|
|
system.cpu0.itb.hits 29573368 # DTB hits
|
|
system.cpu0.itb.misses 2205 # DTB misses
|
|
system.cpu0.itb.accesses 29575573 # DTB accesses
|
|
system.cpu0.numCycles 2365916518 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.committedInsts 28875412 # Number of instructions committed
|
|
system.cpu0.committedOps 37222765 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 33109279 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 1241807 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 4373656 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 33109279 # number of integer instructions
|
|
system.cpu0.num_fp_insts 3860 # number of float instructions
|
|
system.cpu0.num_int_register_reads 190112848 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 36234022 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
|
|
system.cpu0.num_mem_refs 13400902 # number of memory refs
|
|
system.cpu0.num_load_insts 7411207 # Number of load instructions
|
|
system.cpu0.num_store_insts 5989695 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 2224988060.360119 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 140928457.639881 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.059566 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.940434 # Percentage of idle cycles
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 46697 # number of quiesce instructions executed
|
|
system.cpu0.icache.replacements 425482 # number of replacements
|
|
system.cpu0.icache.tagsinuse 509.601890 # Cycle average of tags in use
|
|
system.cpu0.icache.total_refs 29147356 # Total number of references to valid blocks.
|
|
system.cpu0.icache.sampled_refs 425994 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.avg_refs 68.421987 # Average number of references to valid blocks.
|
|
system.cpu0.icache.warmup_cycle 74995953000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.occ_blocks::cpu0.inst 509.601890 # Average occupied blocks per requestor
|
|
system.cpu0.icache.occ_percent::cpu0.inst 0.995316 # Average percentage of cache occupancy
|
|
system.cpu0.icache.occ_percent::total 0.995316 # Average percentage of cache occupancy
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 29147356 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 29147356 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 29147356 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 29147356 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 29147356 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 29147356 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 425995 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 425995 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 425995 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 425995 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 425995 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 425995 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5809941500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 5809941500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 5809941500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 5809941500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 5809941500 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 5809941500 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 29573351 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 29573351 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 29573351 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 29573351 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 29573351 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 29573351 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13638.520405 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 13638.520405 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13638.520405 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 13638.520405 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13638.520405 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 13638.520405 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425995 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 425995 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 425995 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 425995 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 425995 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 425995 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4957951500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4957951500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4957951500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 4957951500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4957951500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 4957951500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 299599000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 299599000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 299599000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 299599000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014405 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.014405 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.014405 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11638.520405 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11638.520405 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11638.520405 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11638.520405 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11638.520405 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11638.520405 # average overall mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.replacements 331027 # number of replacements
|
|
system.cpu0.dcache.tagsinuse 453.640914 # Cycle average of tags in use
|
|
system.cpu0.dcache.total_refs 12276777 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.sampled_refs 331539 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.avg_refs 37.029662 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.warmup_cycle 473552000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.occ_blocks::cpu0.data 453.640914 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.occ_percent::cpu0.data 0.886017 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.occ_percent::total 0.886017 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 6603200 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 6603200 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 5353855 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 5353855 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147936 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 147936 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149699 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 149699 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 11957055 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 11957055 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 11957055 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 11957055 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 228068 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 228068 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 141674 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 141674 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9338 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 9338 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7490 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 7490 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 369742 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 369742 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 369742 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 369742 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3146768000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 3146768000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4132891500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 4132891500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88585500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 88585500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44513500 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 44513500 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 7279659500 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 7279659500 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 7279659500 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 7279659500 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6831268 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 6831268 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495529 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 5495529 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157274 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 157274 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157189 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 157189 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 12326797 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 12326797 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 12326797 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 12326797 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033386 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.033386 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025780 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.025780 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059374 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059374 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047650 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047650 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029995 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.029995 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029995 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.029995 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13797.498992 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13797.498992 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29171.841693 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 29171.841693 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9486.560291 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9486.560291 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5943.057410 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5943.057410 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19688.484132 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 19688.484132 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19688.484132 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 19688.484132 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 306714 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 306714 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228068 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 228068 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141674 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 141674 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9338 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9338 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7487 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7487 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 369742 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 369742 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 369742 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 369742 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2690632000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2690632000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3849543500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3849543500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69909500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69909500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29541500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29541500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6540175500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 6540175500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6540175500 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 6540175500 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13562243000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13562243000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128446000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128446000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14690689000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14690689000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033386 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033386 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025780 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025780 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059374 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059374 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047631 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047631 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029995 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.029995 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029995 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.029995 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11797.498992 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11797.498992 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27171.841693 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27171.841693 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7486.560291 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7486.560291 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3945.705890 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3945.705890 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17688.484132 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17688.484132 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17688.484132 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17688.484132 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 8309714 # DTB read hits
|
|
system.cpu1.dtb.read_misses 3643 # DTB read misses
|
|
system.cpu1.dtb.write_hits 5826503 # DTB write hits
|
|
system.cpu1.dtb.write_misses 1435 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 8313357 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 5827938 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 14136217 # DTB hits
|
|
system.cpu1.dtb.misses 5078 # DTB misses
|
|
system.cpu1.dtb.accesses 14141295 # DTB accesses
|
|
system.cpu1.itb.inst_hits 33189716 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 2171 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 33191887 # ITB inst accesses
|
|
system.cpu1.itb.hits 33189716 # DTB hits
|
|
system.cpu1.itb.misses 2171 # DTB misses
|
|
system.cpu1.itb.accesses 33191887 # DTB accesses
|
|
system.cpu1.numCycles 2364475282 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 32579235 # Number of instructions committed
|
|
system.cpu1.committedOps 41086550 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 37310899 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 962009 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 3732730 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 37310899 # number of integer instructions
|
|
system.cpu1.num_fp_insts 6793 # number of float instructions
|
|
system.cpu1.num_int_register_reads 213650265 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 39453467 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 14673985 # number of memory refs
|
|
system.cpu1.num_load_insts 8631614 # Number of load instructions
|
|
system.cpu1.num_store_insts 6042371 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 1868339828.826306 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 496135453.173694 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.209829 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.790171 # Percentage of idle cycles
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 43883 # number of quiesce instructions executed
|
|
system.cpu1.icache.replacements 469209 # number of replacements
|
|
system.cpu1.icache.tagsinuse 478.755545 # Cycle average of tags in use
|
|
system.cpu1.icache.total_refs 32719991 # Total number of references to valid blocks.
|
|
system.cpu1.icache.sampled_refs 469721 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.avg_refs 69.658353 # Average number of references to valid blocks.
|
|
system.cpu1.icache.warmup_cycle 92137748500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.occ_blocks::cpu1.inst 478.755545 # Average occupied blocks per requestor
|
|
system.cpu1.icache.occ_percent::cpu1.inst 0.935069 # Average percentage of cache occupancy
|
|
system.cpu1.icache.occ_percent::total 0.935069 # Average percentage of cache occupancy
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 32719991 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 32719991 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 32719991 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 32719991 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 32719991 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 32719991 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 469721 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 469721 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 469721 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 469721 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 469721 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 469721 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6363755000 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 6363755000 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 6363755000 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 6363755000 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 6363755000 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 6363755000 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 33189712 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 33189712 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 33189712 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 33189712 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 33189712 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 33189712 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014153 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.014153 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014153 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.014153 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014153 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.014153 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13547.946547 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 13547.946547 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13547.946547 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 13547.946547 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13547.946547 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 13547.946547 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469721 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 469721 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 469721 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 469721 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 469721 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 469721 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5424313000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5424313000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5424313000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 5424313000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5424313000 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 5424313000 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4396000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4396000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4396000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::total 4396000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014153 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.014153 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.014153 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11547.946547 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11547.946547 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11547.946547 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11547.946547 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11547.946547 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11547.946547 # average overall mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.replacements 292184 # number of replacements
|
|
system.cpu1.dcache.tagsinuse 472.133429 # Cycle average of tags in use
|
|
system.cpu1.dcache.total_refs 11959580 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.sampled_refs 292554 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.avg_refs 40.879906 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.warmup_cycle 83709904000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.occ_blocks::cpu1.data 472.133429 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.occ_percent::cpu1.data 0.922136 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.occ_percent::total 0.922136 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 6945060 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 6945060 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 4826351 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 4826351 # number of WriteReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81758 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 81758 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82709 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 82709 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 11771411 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 11771411 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 11771411 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 11771411 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 170725 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 170725 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 149867 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 149867 # number of WriteReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11052 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 11052 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10028 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 10028 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 320592 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 320592 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 320592 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 320592 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2168241500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 2168241500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4524943000 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 4524943000 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92270500 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::total 92270500 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51657000 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::total 51657000 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 6693184500 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 6693184500 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 6693184500 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 6693184500 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 7115785 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 7115785 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 4976218 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 4976218 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92810 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 92810 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92737 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 92737 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 12092003 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 12092003 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 12092003 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 12092003 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023992 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.023992 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030117 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.030117 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119082 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119082 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108134 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108134 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026513 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.026513 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026513 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.026513 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12700.199151 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12700.199151 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30193.057845 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 30193.057845 # average WriteReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8348.760405 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8348.760405 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5151.276426 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5151.276426 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20877.578043 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 20877.578043 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20877.578043 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 20877.578043 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 265550 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 265550 # number of writebacks
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170725 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 170725 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149867 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 149867 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11052 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11052 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10024 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::total 10024 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 320592 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 320592 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 320592 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 320592 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1826791500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1826791500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4225209000 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4225209000 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70166500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70166500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31611000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31611000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6052000500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 6052000500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6052000500 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 6052000500 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168642802500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168642802500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17668343500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17668343500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186311146000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186311146000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023992 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023992 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030117 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030117 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119082 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119082 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108091 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108091 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.026513 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.026513 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10700.199151 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10700.199151 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28193.057845 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28193.057845 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6348.760405 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6348.760405 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3153.531524 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3153.531524 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18877.578043 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18877.578043 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18877.578043 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18877.578043 # average overall mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.replacements 0 # number of replacements
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509685021664 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 509685021664 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509685021664 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 509685021664 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|