1700 lines
192 KiB
Text
1700 lines
192 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 152094 # Simulator instruction rate (inst/s)
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host_mem_usage 214340 # Number of bytes of host memory used
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host_seconds 7.59 # Real time elapsed on the host
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host_tick_rate 15507555 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1153987 # Number of instructions simulated
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sim_seconds 0.000118 # Number of seconds simulated
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sim_ticks 117665000 # Number of ticks simulated
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system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu0.BPredUnit.BTBHits 89393 # Number of BTB hits
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system.cpu0.BPredUnit.BTBLookups 92028 # Number of BTB lookups
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system.cpu0.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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system.cpu0.BPredUnit.condIncorrect 1075 # Number of conditional branches incorrect
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system.cpu0.BPredUnit.condPredicted 92481 # Number of conditional branches predicted
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system.cpu0.BPredUnit.lookups 92481 # Number of BP lookups
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system.cpu0.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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system.cpu0.commit.COM:branches 89667 # Number of branches committed
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system.cpu0.commit.COM:bw_lim_events 218 # number cycles where commit BW limit reached
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system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu0.commit.COM:committed_per_cycle::samples 215178 # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::mean 2.487387 # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::stdev 2.121699 # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::0 33843 15.73% 15.73% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::1 90761 42.18% 57.91% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::2 2490 1.16% 59.06% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::3 739 0.34% 59.41% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::4 743 0.35% 59.75% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::5 85822 39.88% 99.64% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::6 487 0.23% 99.86% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::7 75 0.03% 99.90% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::8 218 0.10% 100.00% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::total 215178 # Number of insts commited each cycle
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system.cpu0.commit.COM:count 535231 # Number of instructions committed
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system.cpu0.commit.COM:loads 174546 # Number of loads committed
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system.cpu0.commit.COM:membars 84 # Number of memory barriers committed
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system.cpu0.commit.COM:refs 262325 # Number of memory references committed
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system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu0.commit.branchMispredicts 1075 # The number of times a branch was mispredicted
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system.cpu0.commit.commitCommittedInsts 535231 # The number of committed instructions
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system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
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system.cpu0.commit.commitSquashedInsts 9532 # The number of squashed insts skipped by commit
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system.cpu0.committedInsts 448749 # Number of Instructions Simulated
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system.cpu0.committedInsts_total 448749 # Number of Instructions Simulated
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system.cpu0.cpi 0.524416 # CPI: Cycles Per Instruction
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system.cpu0.cpi_total 0.524416 # CPI: Total CPI of All Threads
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system.cpu0.dcache.ReadReq_accesses 89627 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_avg_miss_latency 27580.808081 # average ReadReq miss latency
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system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27913.043478 # average ReadReq mshr miss latency
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system.cpu0.dcache.ReadReq_hits 89132 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_miss_latency 13652500 # number of ReadReq miss cycles
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system.cpu0.dcache.ReadReq_miss_rate 0.005523 # miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_misses 495 # number of ReadReq misses
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system.cpu0.dcache.ReadReq_mshr_hits 311 # number of ReadReq MSHR hits
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system.cpu0.dcache.ReadReq_mshr_miss_latency 5136000 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002053 # mshr miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_mshr_misses 184 # number of ReadReq MSHR misses
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system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses)
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system.cpu0.dcache.SwapReq_avg_miss_latency 16596.153846 # average SwapReq miss latency
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system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 13596.153846 # average SwapReq mshr miss latency
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system.cpu0.dcache.SwapReq_hits 16 # number of SwapReq hits
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system.cpu0.dcache.SwapReq_miss_latency 431500 # number of SwapReq miss cycles
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system.cpu0.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses
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system.cpu0.dcache.SwapReq_misses 26 # number of SwapReq misses
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system.cpu0.dcache.SwapReq_mshr_miss_latency 353500 # number of SwapReq MSHR miss cycles
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system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses
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system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses
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system.cpu0.dcache.WriteReq_accesses 87737 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_avg_miss_latency 46115.711111 # average WriteReq miss latency
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system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 37137.931034 # average WriteReq mshr miss latency
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system.cpu0.dcache.WriteReq_hits 87197 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_miss_latency 24902484 # number of WriteReq miss cycles
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system.cpu0.dcache.WriteReq_miss_rate 0.006155 # miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_misses 540 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_mshr_hits 366 # number of WriteReq MSHR hits
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system.cpu0.dcache.WriteReq_mshr_miss_latency 6462000 # number of WriteReq MSHR miss cycles
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system.cpu0.dcache.WriteReq_mshr_miss_rate 0.001983 # mshr miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses
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system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8595.238095 # average number of cycles each access was blocked
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system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu0.dcache.avg_refs 640.367816 # Average number of references to valid blocks.
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system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles::no_mshrs 180500 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.demand_accesses 177364 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_avg_miss_latency 37251.192271 # average overall miss latency
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system.cpu0.dcache.demand_avg_mshr_miss_latency 32396.648045 # average overall mshr miss latency
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system.cpu0.dcache.demand_hits 176329 # number of demand (read+write) hits
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system.cpu0.dcache.demand_miss_latency 38554984 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_miss_rate 0.005835 # miss rate for demand accesses
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system.cpu0.dcache.demand_misses 1035 # number of demand (read+write) misses
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system.cpu0.dcache.demand_mshr_hits 677 # number of demand (read+write) MSHR hits
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system.cpu0.dcache.demand_mshr_miss_latency 11598000 # number of demand (read+write) MSHR miss cycles
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system.cpu0.dcache.demand_mshr_miss_rate 0.002018 # mshr miss rate for demand accesses
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system.cpu0.dcache.demand_mshr_misses 358 # number of demand (read+write) MSHR misses
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.dcache.occ_%::0 0.275981 # Average percentage of cache occupancy
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system.cpu0.dcache.occ_%::1 -0.002700 # Average percentage of cache occupancy
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system.cpu0.dcache.occ_blocks::0 141.302499 # Average occupied blocks per context
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system.cpu0.dcache.occ_blocks::1 -1.382442 # Average occupied blocks per context
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system.cpu0.dcache.overall_accesses 177364 # number of overall (read+write) accesses
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system.cpu0.dcache.overall_avg_miss_latency 37251.192271 # average overall miss latency
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system.cpu0.dcache.overall_avg_mshr_miss_latency 32396.648045 # average overall mshr miss latency
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system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu0.dcache.overall_hits 176329 # number of overall hits
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system.cpu0.dcache.overall_miss_latency 38554984 # number of overall miss cycles
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system.cpu0.dcache.overall_miss_rate 0.005835 # miss rate for overall accesses
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system.cpu0.dcache.overall_misses 1035 # number of overall misses
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system.cpu0.dcache.overall_mshr_hits 677 # number of overall MSHR hits
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system.cpu0.dcache.overall_mshr_miss_latency 11598000 # number of overall MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_rate 0.002018 # mshr miss rate for overall accesses
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system.cpu0.dcache.overall_mshr_misses 358 # number of overall MSHR misses
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system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu0.dcache.replacements 9 # number of replacements
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system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks.
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system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu0.dcache.tagsinuse 139.920057 # Cycle average of tags in use
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system.cpu0.dcache.total_refs 111424 # Total number of references to valid blocks.
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system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.writebacks 6 # number of writebacks
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system.cpu0.decode.DECODE:BlockedCycles 13620 # Number of cycles decode is blocked
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system.cpu0.decode.DECODE:DecodedInsts 549750 # Number of instructions handled by decode
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system.cpu0.decode.DECODE:IdleCycles 20029 # Number of cycles decode is idle
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system.cpu0.decode.DECODE:RunCycles 181310 # Number of cycles decode is running
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system.cpu0.decode.DECODE:SquashCycles 2059 # Number of cycles decode is squashing
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system.cpu0.decode.DECODE:UnblockCycles 202 # Number of cycles decode is unblocking
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system.cpu0.fetch.Branches 92481 # Number of branches that fetch encountered
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system.cpu0.fetch.CacheLines 5258 # Number of cache lines fetched
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system.cpu0.fetch.Cycles 187053 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu0.fetch.IcacheSquashes 482 # Number of outstanding Icache misses that were squashed
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system.cpu0.fetch.Insts 550749 # Number of instructions fetch has processed
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system.cpu0.fetch.SquashCycles 1232 # Number of cycles fetch has spent squashing
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system.cpu0.fetch.branchRate 0.392983 # Number of branch fetches per cycle
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system.cpu0.fetch.icacheStallCycles 5258 # Number of cycles fetch is stalled on an Icache miss
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system.cpu0.fetch.predictedBranches 89393 # Number of branches that fetch has predicted taken
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system.cpu0.fetch.rate 2.340316 # Number of inst fetches per cycle
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system.cpu0.fetch.rateDist::samples 217220 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::mean 2.535443 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::stdev 2.186868 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::0 35466 16.33% 16.33% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::1 90305 41.57% 57.90% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::2 487 0.22% 58.12% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::3 806 0.37% 58.50% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::4 587 0.27% 58.77% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::5 86662 39.90% 98.66% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::6 826 0.38% 99.04% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::7 210 0.10% 99.14% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::8 1871 0.86% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::total 217220 # Number of instructions fetched each cycle (Total)
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system.cpu0.icache.ReadReq_accesses 5258 # number of ReadReq accesses(hits+misses)
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system.cpu0.icache.ReadReq_avg_miss_latency 39105.298013 # average ReadReq miss latency
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system.cpu0.icache.ReadReq_avg_mshr_miss_latency 37007.389163 # average ReadReq mshr miss latency
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system.cpu0.icache.ReadReq_hits 4503 # number of ReadReq hits
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system.cpu0.icache.ReadReq_miss_latency 29524500 # number of ReadReq miss cycles
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system.cpu0.icache.ReadReq_miss_rate 0.143591 # miss rate for ReadReq accesses
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system.cpu0.icache.ReadReq_misses 755 # number of ReadReq misses
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system.cpu0.icache.ReadReq_mshr_hits 146 # number of ReadReq MSHR hits
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system.cpu0.icache.ReadReq_mshr_miss_latency 22537500 # number of ReadReq MSHR miss cycles
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system.cpu0.icache.ReadReq_mshr_miss_rate 0.115824 # mshr miss rate for ReadReq accesses
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system.cpu0.icache.ReadReq_mshr_misses 609 # number of ReadReq MSHR misses
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system.cpu0.icache.avg_blocked_cycles::no_mshrs 11000 # average number of cycles each access was blocked
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system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu0.icache.avg_refs 7.406250 # Average number of references to valid blocks.
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system.cpu0.icache.blocked::no_mshrs 2 # number of cycles access was blocked
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system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.blocked_cycles::no_mshrs 22000 # number of cycles access was blocked
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system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.cache_copies 0 # number of cache copies performed
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system.cpu0.icache.demand_accesses 5258 # number of demand (read+write) accesses
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system.cpu0.icache.demand_avg_miss_latency 39105.298013 # average overall miss latency
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system.cpu0.icache.demand_avg_mshr_miss_latency 37007.389163 # average overall mshr miss latency
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system.cpu0.icache.demand_hits 4503 # number of demand (read+write) hits
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system.cpu0.icache.demand_miss_latency 29524500 # number of demand (read+write) miss cycles
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system.cpu0.icache.demand_miss_rate 0.143591 # miss rate for demand accesses
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system.cpu0.icache.demand_misses 755 # number of demand (read+write) misses
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system.cpu0.icache.demand_mshr_hits 146 # number of demand (read+write) MSHR hits
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system.cpu0.icache.demand_mshr_miss_latency 22537500 # number of demand (read+write) MSHR miss cycles
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system.cpu0.icache.demand_mshr_miss_rate 0.115824 # mshr miss rate for demand accesses
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system.cpu0.icache.demand_mshr_misses 609 # number of demand (read+write) MSHR misses
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system.cpu0.icache.fast_writes 0 # number of fast writes performed
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|
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.occ_%::0 0.502905 # Average percentage of cache occupancy
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|
system.cpu0.icache.occ_blocks::0 257.487512 # Average occupied blocks per context
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|
system.cpu0.icache.overall_accesses 5258 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_avg_miss_latency 39105.298013 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency 37007.389163 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu0.icache.overall_hits 4503 # number of overall hits
|
|
system.cpu0.icache.overall_miss_latency 29524500 # number of overall miss cycles
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system.cpu0.icache.overall_miss_rate 0.143591 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_misses 755 # number of overall misses
|
|
system.cpu0.icache.overall_mshr_hits 146 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_miss_latency 22537500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_rate 0.115824 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_misses 609 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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|
system.cpu0.icache.replacements 307 # number of replacements
|
|
system.cpu0.icache.sampled_refs 608 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu0.icache.tagsinuse 257.487512 # Cycle average of tags in use
|
|
system.cpu0.icache.total_refs 4503 # Total number of references to valid blocks.
|
|
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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|
system.cpu0.icache.writebacks 0 # number of writebacks
|
|
system.cpu0.idleCycles 18111 # Total number of cycles that the CPU has spent unscheduled due to idling
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|
system.cpu0.iew.EXEC:branches 90461 # Number of branches executed
|
|
system.cpu0.iew.EXEC:nop 86855 # number of nop insts executed
|
|
system.cpu0.iew.EXEC:rate 1.931679 # Inst execution rate
|
|
system.cpu0.iew.EXEC:refs 263994 # number of memory reference insts executed
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|
system.cpu0.iew.EXEC:stores 88313 # Number of stores executed
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|
system.cpu0.iew.EXEC:swp 0 # number of swp insts executed
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|
system.cpu0.iew.WB:consumers 271356 # num instructions consuming a value
|
|
system.cpu0.iew.WB:count 453956 # cumulative count of insts written-back
|
|
system.cpu0.iew.WB:fanout 0.992932 # average fanout of values written-back
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|
system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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|
system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu0.iew.WB:producers 269438 # num instructions producing a value
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|
system.cpu0.iew.WB:rate 1.929011 # insts written-back per cycle
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|
system.cpu0.iew.WB:sent 454201 # cumulative count of insts sent to commit
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|
system.cpu0.iew.branchMispredicts 1256 # Number of branch mispredicts detected at execute
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|
system.cpu0.iew.iewBlockCycles 901 # Number of cycles IEW is blocking
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|
system.cpu0.iew.iewDispLoadInsts 176230 # Number of dispatched load instructions
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system.cpu0.iew.iewDispNonSpecInsts 725 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewDispSquashedInsts 482 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispStoreInsts 88858 # Number of dispatched store instructions
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|
system.cpu0.iew.iewDispatchedInsts 544759 # Number of instructions dispatched to IQ
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|
system.cpu0.iew.iewExecLoadInsts 175681 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 928 # Number of squashed instructions skipped in execute
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system.cpu0.iew.iewExecutedInsts 454584 # Number of executed instructions
|
|
system.cpu0.iew.iewIQFullEvents 25 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.iewSquashCycles 2059 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewUnblockCycles 26 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread.0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.lsq.thread.0.forwLoads 86003 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread.0.memOrderViolation 74 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread.0.squashedLoads 1684 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread.0.squashedStores 1079 # Number of stores squashed
|
|
system.cpu0.iew.memOrderViolationEvents 74 # Number of memory order violations
|
|
system.cpu0.iew.predictedNotTakenIncorrect 831 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.predictedTakenIncorrect 425 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.ipc 1.906884 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 1.906884 # IPC: Total IPC of All Threads
|
|
system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::IntAlu 191111 41.96% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::IntMult 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 41.96% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::MemRead 175974 38.63% 80.59% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::MemWrite 88427 19.41% 100.00% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::total 455512 # Type of FU issued
|
|
system.cpu0.iq.ISSUE:fu_busy_cnt 219 # FU busy when requested
|
|
system.cpu0.iq.ISSUE:fu_busy_rate 0.000481 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::IntAlu 29 13.24% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 13.24% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::MemRead 83 37.90% 51.14% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::MemWrite 107 48.86% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::samples 217220 # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::mean 2.097008 # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.057658 # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::0 33500 15.42% 15.42% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::1 5647 2.60% 18.02% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::2 88284 40.64% 58.66% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::3 87260 40.17% 98.84% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::4 1518 0.70% 99.53% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::5 727 0.33% 99.87% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::6 185 0.09% 99.95% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::7 92 0.04% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::8 7 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::total 217220 # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:rate 1.935623 # Inst issue rate
|
|
system.cpu0.iq.iqInstsAdded 457082 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqInstsIssued 455512 # Number of instructions issued
|
|
system.cpu0.iq.iqNonSpecInstsAdded 822 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqSquashedInstsExamined 8244 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedInstsIssued 90 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 263 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.iqSquashedOperandsExamined 6884 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.memDep0.conflictingLoads 86366 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 86212 # Number of conflicting stores.
|
|
system.cpu0.memDep0.insertedLoads 176230 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 88858 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.numCycles 235331 # number of cpu cycles simulated
|
|
system.cpu0.rename.RENAME:BlockCycles 1287 # Number of cycles rename is blocking
|
|
system.cpu0.rename.RENAME:CommittedMaps 361924 # Number of HB maps that are committed
|
|
system.cpu0.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full
|
|
system.cpu0.rename.RENAME:IdleCycles 20717 # Number of cycles rename is idle
|
|
system.cpu0.rename.RENAME:LSQFullEvents 290 # Number of times rename has blocked due to LSQ full
|
|
system.cpu0.rename.RENAME:RenameLookups 1091002 # Number of register rename lookups that rename has made
|
|
system.cpu0.rename.RENAME:RenamedInsts 546581 # Number of instructions processed by rename
|
|
system.cpu0.rename.RENAME:RenamedOperands 372241 # Number of destination operands rename has renamed
|
|
system.cpu0.rename.RENAME:RunCycles 180866 # Number of cycles rename is running
|
|
system.cpu0.rename.RENAME:SquashCycles 2059 # Number of cycles rename is squashing
|
|
system.cpu0.rename.RENAME:UnblockCycles 696 # Number of cycles rename is unblocking
|
|
system.cpu0.rename.RENAME:UndoneMaps 10317 # Number of HB maps that are undone due to squashing
|
|
system.cpu0.rename.RENAME:serializeStallCycles 11595 # count of cycles rename stalled for serializing inst
|
|
system.cpu0.rename.RENAME:serializingInsts 810 # count of serializing insts renamed
|
|
system.cpu0.rename.RENAME:skidInsts 4205 # count of insts added to the skid buffer
|
|
system.cpu0.rename.RENAME:tempSerializingInsts 813 # count of temporary serializing insts renamed
|
|
system.cpu0.timesIdled 337 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls
|
|
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.BPredUnit.BTBHits 54164 # Number of BTB hits
|
|
system.cpu1.BPredUnit.BTBLookups 56398 # Number of BTB lookups
|
|
system.cpu1.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
|
system.cpu1.BPredUnit.condIncorrect 1087 # Number of conditional branches incorrect
|
|
system.cpu1.BPredUnit.condPredicted 56510 # Number of conditional branches predicted
|
|
system.cpu1.BPredUnit.lookups 56510 # Number of BP lookups
|
|
system.cpu1.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
|
system.cpu1.commit.COM:branches 53699 # Number of branches committed
|
|
system.cpu1.commit.COM:bw_lim_events 485 # number cycles where commit BW limit reached
|
|
system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu1.commit.COM:committed_per_cycle::samples 188517 # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::mean 1.608476 # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::stdev 1.965365 # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::0 76809 40.74% 40.74% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::1 54523 28.92% 69.67% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::2 7469 3.96% 73.63% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::3 7247 3.84% 77.47% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::4 2461 1.31% 78.78% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::5 38972 20.67% 99.45% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::6 418 0.22% 99.67% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::7 133 0.07% 99.74% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::8 485 0.26% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::total 188517 # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:count 303225 # Number of instructions committed
|
|
system.cpu1.commit.COM:loads 89251 # Number of loads committed
|
|
system.cpu1.commit.COM:membars 5705 # Number of memory barriers committed
|
|
system.cpu1.commit.COM:refs 131280 # Number of memory references committed
|
|
system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.branchMispredicts 1087 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.commitCommittedInsts 303225 # The number of committed instructions
|
|
system.cpu1.commit.commitNonSpecStalls 6419 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.commitSquashedInsts 8275 # The number of squashed insts skipped by commit
|
|
system.cpu1.committedInsts 253031 # Number of Instructions Simulated
|
|
system.cpu1.committedInsts_total 253031 # Number of Instructions Simulated
|
|
system.cpu1.cpi 0.791401 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 0.791401 # CPI: Total CPI of All Threads
|
|
system.cpu1.dcache.ReadReq_accesses 51825 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency 22044.372294 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13760.869565 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_hits 51363 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_miss_latency 10184500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_rate 0.008915 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_misses 462 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_mshr_hits 301 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency 2215500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate 0.003107 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_misses 161 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_accesses 68 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency 25285.714286 # average SwapReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 22285.714286 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_hits 12 # number of SwapReq hits
|
|
system.cpu1.dcache.SwapReq_miss_latency 1416000 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_rate 0.823529 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_misses 56 # number of SwapReq misses
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency 1248000 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate 0.823529 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_misses 56 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_accesses 41961 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency 22944 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 14406.542056 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_hits 41836 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_miss_latency 2868000 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_rate 0.002979 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_misses 125 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency 1541500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002550 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_misses 107 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_refs 1593.333333 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.demand_accesses 93786 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_avg_miss_latency 22235.945486 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency 14018.656716 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_hits 93199 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_miss_latency 13052500 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_rate 0.006259 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_misses 587 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_miss_latency 3757000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_rate 0.002858 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_misses 268 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.occ_%::0 0.047197 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.occ_%::1 -0.018851 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.occ_blocks::0 24.164747 # Average occupied blocks per context
|
|
system.cpu1.dcache.occ_blocks::1 -9.651740 # Average occupied blocks per context
|
|
system.cpu1.dcache.overall_accesses 93786 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_avg_miss_latency 22235.945486 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency 14018.656716 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_hits 93199 # number of overall hits
|
|
system.cpu1.dcache.overall_miss_latency 13052500 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_rate 0.006259 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_misses 587 # number of overall misses
|
|
system.cpu1.dcache.overall_mshr_hits 319 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_miss_latency 3757000 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_rate 0.002858 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_misses 268 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu1.dcache.replacements 2 # number of replacements
|
|
system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu1.dcache.tagsinuse 14.513007 # Cycle average of tags in use
|
|
system.cpu1.dcache.total_refs 47800 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.writebacks 1 # number of writebacks
|
|
system.cpu1.decode.DECODE:BlockedCycles 20785 # Number of cycles decode is blocked
|
|
system.cpu1.decode.DECODE:DecodedInsts 315548 # Number of instructions handled by decode
|
|
system.cpu1.decode.DECODE:IdleCycles 53596 # Number of cycles decode is idle
|
|
system.cpu1.decode.DECODE:RunCycles 108904 # Number of cycles decode is running
|
|
system.cpu1.decode.DECODE:SquashCycles 1778 # Number of cycles decode is squashing
|
|
system.cpu1.decode.DECODE:UnblockCycles 5231 # Number of cycles decode is unblocking
|
|
system.cpu1.fetch.Branches 56510 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.CacheLines 20132 # Number of cache lines fetched
|
|
system.cpu1.fetch.Cycles 134664 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.IcacheSquashes 220 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.Insts 316686 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.SquashCycles 1166 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.branchRate 0.282199 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.icacheStallCycles 20132 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.predictedBranches 54164 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.rate 1.581461 # Number of inst fetches per cycle
|
|
system.cpu1.fetch.rateDist::samples 196924 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 1.608164 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 2.050823 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 82414 41.85% 41.85% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 58905 29.91% 71.76% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 6768 3.44% 75.20% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 2772 1.41% 76.61% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::4 1900 0.96% 77.57% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::5 39920 20.27% 97.84% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::6 2488 1.26% 99.11% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::7 255 0.13% 99.24% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::8 1502 0.76% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 196924 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.icache.ReadReq_accesses 20132 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_avg_miss_latency 15221.991701 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12289.237668 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_hits 19650 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_miss_latency 7337000 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_rate 0.023942 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_misses 482 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_mshr_hits 36 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency 5481000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate 0.022154 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_misses 446 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_refs 44.058296 # Average number of references to valid blocks.
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.demand_accesses 20132 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_avg_miss_latency 15221.991701 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency 12289.237668 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_hits 19650 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_miss_latency 7337000 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_rate 0.023942 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_misses 482 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_mshr_hits 36 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.demand_mshr_miss_latency 5481000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_rate 0.022154 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.occ_%::0 0.166450 # Average percentage of cache occupancy
|
|
system.cpu1.icache.occ_blocks::0 85.222348 # Average occupied blocks per context
|
|
system.cpu1.icache.overall_accesses 20132 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_avg_miss_latency 15221.991701 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency 12289.237668 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu1.icache.overall_hits 19650 # number of overall hits
|
|
system.cpu1.icache.overall_miss_latency 7337000 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_rate 0.023942 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_misses 482 # number of overall misses
|
|
system.cpu1.icache.overall_mshr_hits 36 # number of overall MSHR hits
|
|
system.cpu1.icache.overall_mshr_miss_latency 5481000 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_rate 0.022154 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_misses 446 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu1.icache.replacements 334 # number of replacements
|
|
system.cpu1.icache.sampled_refs 446 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu1.icache.tagsinuse 85.222348 # Cycle average of tags in use
|
|
system.cpu1.icache.total_refs 19650 # Total number of references to valid blocks.
|
|
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.writebacks 0 # number of writebacks
|
|
system.cpu1.idleCycles 3325 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.iew.EXEC:branches 54259 # Number of branches executed
|
|
system.cpu1.iew.EXEC:nop 45275 # number of nop insts executed
|
|
system.cpu1.iew.EXEC:rate 1.310923 # Inst execution rate
|
|
system.cpu1.iew.EXEC:refs 132378 # number of memory reference insts executed
|
|
system.cpu1.iew.EXEC:stores 42378 # Number of stores executed
|
|
system.cpu1.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu1.iew.WB:consumers 152453 # num instructions consuming a value
|
|
system.cpu1.iew.WB:count 262146 # cumulative count of insts written-back
|
|
system.cpu1.iew.WB:fanout 0.975993 # average fanout of values written-back
|
|
system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu1.iew.WB:producers 148793 # num instructions producing a value
|
|
system.cpu1.iew.WB:rate 1.309100 # insts written-back per cycle
|
|
system.cpu1.iew.WB:sent 262278 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.branchMispredicts 1189 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewBlockCycles 1723 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewDispLoadInsts 90759 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 936 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewDispSquashedInsts 579 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispStoreInsts 42808 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispatchedInsts 311533 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewExecLoadInsts 90000 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 943 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.iewExecutedInsts 262511 # Number of executed instructions
|
|
system.cpu1.iew.iewIQFullEvents 48 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.iewSquashCycles 1778 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.lsq.thread.0.forwLoads 38160 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread.0.memOrderViolation 37 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread.0.squashedLoads 1508 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread.0.squashedStores 779 # Number of stores squashed
|
|
system.cpu1.iew.memOrderViolationEvents 37 # Number of memory order violations
|
|
system.cpu1.iew.predictedNotTakenIncorrect 207 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.predictedTakenIncorrect 982 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.ipc 1.263582 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 1.263582 # IPC: Total IPC of All Threads
|
|
system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::IntAlu 125153 47.50% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 47.50% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::MemRead 95890 36.40% 83.90% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::MemWrite 42411 16.10% 100.00% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::total 263454 # Type of FU issued
|
|
system.cpu1.iq.ISSUE:fu_busy_cnt 196 # FU busy when requested
|
|
system.cpu1.iq.ISSUE:fu_busy_rate 0.000744 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::IntAlu 10 5.10% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.10% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::MemRead 55 28.06% 33.16% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::MemWrite 131 66.84% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::samples 196924 # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::mean 1.337846 # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.287201 # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::0 78523 39.87% 39.87% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::1 26788 13.60% 53.48% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::2 44704 22.70% 76.18% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::3 42538 21.60% 97.78% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::4 2558 1.30% 99.08% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::5 1568 0.80% 99.88% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::6 153 0.08% 99.95% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::7 82 0.04% 99.99% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::8 10 0.01% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::total 196924 # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:rate 1.315632 # Inst issue rate
|
|
system.cpu1.iq.iqInstsAdded 259237 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqInstsIssued 263454 # Number of instructions issued
|
|
system.cpu1.iq.iqNonSpecInstsAdded 7021 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqSquashedInstsExamined 6583 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.iqSquashedOperandsExamined 6195 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.memDep0.conflictingLoads 44385 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 38318 # Number of conflicting stores.
|
|
system.cpu1.memDep0.insertedLoads 90759 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 42808 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.numCycles 200249 # number of cpu cycles simulated
|
|
system.cpu1.rename.RENAME:BlockCycles 7062 # Number of cycles rename is blocking
|
|
system.cpu1.rename.RENAME:CommittedMaps 207913 # Number of HB maps that are committed
|
|
system.cpu1.rename.RENAME:IQFullEvents 85 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.RENAME:IdleCycles 54227 # Number of cycles rename is idle
|
|
system.cpu1.rename.RENAME:LSQFullEvents 50 # Number of times rename has blocked due to LSQ full
|
|
system.cpu1.rename.RENAME:RenameLookups 600696 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.RENAME:RenamedInsts 313742 # Number of instructions processed by rename
|
|
system.cpu1.rename.RENAME:RenamedOperands 216202 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RENAME:RunCycles 113632 # Number of cycles rename is running
|
|
system.cpu1.rename.RENAME:SquashCycles 1778 # Number of cycles rename is squashing
|
|
system.cpu1.rename.RENAME:UnblockCycles 643 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RENAME:UndoneMaps 8289 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.RENAME:serializeStallCycles 12952 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RENAME:serializingInsts 960 # count of serializing insts renamed
|
|
system.cpu1.rename.RENAME:skidInsts 2963 # count of insts added to the skid buffer
|
|
system.cpu1.rename.RENAME:tempSerializingInsts 1012 # count of temporary serializing insts renamed
|
|
system.cpu1.timesIdled 296 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu2.BPredUnit.BTBHits 47901 # Number of BTB hits
|
|
system.cpu2.BPredUnit.BTBLookups 50093 # Number of BTB lookups
|
|
system.cpu2.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
|
system.cpu2.BPredUnit.condIncorrect 1085 # Number of conditional branches incorrect
|
|
system.cpu2.BPredUnit.condPredicted 50192 # Number of conditional branches predicted
|
|
system.cpu2.BPredUnit.lookups 50192 # Number of BP lookups
|
|
system.cpu2.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
|
system.cpu2.commit.COM:branches 47506 # Number of branches committed
|
|
system.cpu2.commit.COM:bw_lim_events 498 # number cycles where commit BW limit reached
|
|
system.cpu2.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu2.commit.COM:committed_per_cycle::samples 185809 # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::mean 1.418279 # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::stdev 1.887696 # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::0 86613 46.61% 46.61% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::1 48206 25.94% 72.56% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::2 7461 4.02% 76.57% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::3 8520 4.59% 81.16% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::4 2453 1.32% 82.48% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::5 31433 16.92% 99.40% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::6 495 0.27% 99.66% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::7 130 0.07% 99.73% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::8 498 0.27% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:committed_per_cycle::total 185809 # Number of insts commited each cycle
|
|
system.cpu2.commit.COM:count 263529 # Number of instructions committed
|
|
system.cpu2.commit.COM:loads 75595 # Number of loads committed
|
|
system.cpu2.commit.COM:membars 6984 # Number of memory barriers committed
|
|
system.cpu2.commit.COM:refs 110158 # Number of memory references committed
|
|
system.cpu2.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu2.commit.branchMispredicts 1085 # The number of times a branch was mispredicted
|
|
system.cpu2.commit.commitCommittedInsts 263529 # The number of committed instructions
|
|
system.cpu2.commit.commitNonSpecStalls 7697 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu2.commit.commitSquashedInsts 7885 # The number of squashed insts skipped by commit
|
|
system.cpu2.committedInsts 218248 # Number of Instructions Simulated
|
|
system.cpu2.committedInsts_total 218248 # Number of Instructions Simulated
|
|
system.cpu2.cpi 0.916192 # CPI: Cycles Per Instruction
|
|
system.cpu2.cpi_total 0.916192 # CPI: Total CPI of All Threads
|
|
system.cpu2.dcache.ReadReq_accesses 45615 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency 22462.882096 # average ReadReq miss latency
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 15906.060606 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.ReadReq_hits 45157 # number of ReadReq hits
|
|
system.cpu2.dcache.ReadReq_miss_latency 10288000 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.ReadReq_miss_rate 0.010041 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_misses 458 # number of ReadReq misses
|
|
system.cpu2.dcache.ReadReq_mshr_hits 293 # number of ReadReq MSHR hits
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency 2624500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003617 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_mshr_misses 165 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_accesses 67 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency 27057.692308 # average SwapReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 24057.692308 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_hits 15 # number of SwapReq hits
|
|
system.cpu2.dcache.SwapReq_miss_latency 1407000 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_rate 0.776119 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_misses 52 # number of SwapReq misses
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency 1251000 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate 0.776119 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_misses 52 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_accesses 34496 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency 24833.333333 # average WriteReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16634.615385 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_hits 34373 # number of WriteReq hits
|
|
system.cpu2.dcache.WriteReq_miss_latency 3054500 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_rate 0.003566 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_misses 123 # number of WriteReq misses
|
|
system.cpu2.dcache.WriteReq_mshr_hits 19 # number of WriteReq MSHR hits
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency 1730000 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate 0.003015 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_misses 104 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu2.dcache.avg_refs 1343.133333 # Average number of references to valid blocks.
|
|
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.dcache.demand_accesses 80111 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.demand_avg_miss_latency 22964.716007 # average overall miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency 16187.732342 # average overall mshr miss latency
|
|
system.cpu2.dcache.demand_hits 79530 # number of demand (read+write) hits
|
|
system.cpu2.dcache.demand_miss_latency 13342500 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.demand_miss_rate 0.007252 # miss rate for demand accesses
|
|
system.cpu2.dcache.demand_misses 581 # number of demand (read+write) misses
|
|
system.cpu2.dcache.demand_mshr_hits 312 # number of demand (read+write) MSHR hits
|
|
system.cpu2.dcache.demand_mshr_miss_latency 4354500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_rate 0.003358 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.demand_mshr_misses 269 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.dcache.occ_%::0 0.052845 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.occ_%::1 -0.017028 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.occ_blocks::0 27.056623 # Average occupied blocks per context
|
|
system.cpu2.dcache.occ_blocks::1 -8.718285 # Average occupied blocks per context
|
|
system.cpu2.dcache.overall_accesses 80111 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.overall_avg_miss_latency 22964.716007 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency 16187.732342 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu2.dcache.overall_hits 79530 # number of overall hits
|
|
system.cpu2.dcache.overall_miss_latency 13342500 # number of overall miss cycles
|
|
system.cpu2.dcache.overall_miss_rate 0.007252 # miss rate for overall accesses
|
|
system.cpu2.dcache.overall_misses 581 # number of overall misses
|
|
system.cpu2.dcache.overall_mshr_hits 312 # number of overall MSHR hits
|
|
system.cpu2.dcache.overall_mshr_miss_latency 4354500 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_rate 0.003358 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.overall_mshr_misses 269 # number of overall MSHR misses
|
|
system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu2.dcache.replacements 2 # number of replacements
|
|
system.cpu2.dcache.sampled_refs 30 # Sample count of references to valid blocks.
|
|
system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu2.dcache.tagsinuse 18.338338 # Cycle average of tags in use
|
|
system.cpu2.dcache.total_refs 40294 # Total number of references to valid blocks.
|
|
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.dcache.writebacks 1 # number of writebacks
|
|
system.cpu2.decode.DECODE:BlockedCycles 22122 # Number of cycles decode is blocked
|
|
system.cpu2.decode.DECODE:DecodedInsts 275316 # Number of instructions handled by decode
|
|
system.cpu2.decode.DECODE:IdleCycles 60659 # Number of cycles decode is idle
|
|
system.cpu2.decode.DECODE:RunCycles 96539 # Number of cycles decode is running
|
|
system.cpu2.decode.DECODE:SquashCycles 1720 # Number of cycles decode is squashing
|
|
system.cpu2.decode.DECODE:UnblockCycles 6488 # Number of cycles decode is unblocking
|
|
system.cpu2.fetch.Branches 50192 # Number of branches that fetch encountered
|
|
system.cpu2.fetch.CacheLines 22953 # Number of cache lines fetched
|
|
system.cpu2.fetch.Cycles 126374 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu2.fetch.IcacheSquashes 220 # Number of outstanding Icache misses that were squashed
|
|
system.cpu2.fetch.Insts 276443 # Number of instructions fetch has processed
|
|
system.cpu2.fetch.SquashCycles 1163 # Number of cycles fetch has spent squashing
|
|
system.cpu2.fetch.branchRate 0.251014 # Number of branch fetches per cycle
|
|
system.cpu2.fetch.icacheStallCycles 22953 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu2.fetch.predictedBranches 47901 # Number of branches that fetch has predicted taken
|
|
system.cpu2.fetch.rate 1.382512 # Number of inst fetches per cycle
|
|
system.cpu2.fetch.rateDist::samples 194140 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::mean 1.423936 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::stdev 1.970541 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::0 90749 46.74% 46.74% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::1 54056 27.84% 74.59% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::2 8214 4.23% 78.82% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::3 2581 1.33% 80.15% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::4 1900 0.98% 81.13% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::5 32436 16.71% 97.83% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::6 2464 1.27% 99.10% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::7 268 0.14% 99.24% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::8 1472 0.76% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::total 194140 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.icache.ReadReq_accesses 22953 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.ReadReq_avg_miss_latency 21650 # average ReadReq miss latency
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18383.484163 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.ReadReq_hits 22463 # number of ReadReq hits
|
|
system.cpu2.icache.ReadReq_miss_latency 10608500 # number of ReadReq miss cycles
|
|
system.cpu2.icache.ReadReq_miss_rate 0.021348 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_misses 490 # number of ReadReq misses
|
|
system.cpu2.icache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency 8125500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate 0.019257 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_mshr_misses 442 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.avg_blocked_cycles::no_mshrs 18250 # average number of cycles each access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu2.icache.avg_refs 50.821267 # Average number of references to valid blocks.
|
|
system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked_cycles::no_mshrs 36500 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.icache.demand_accesses 22953 # number of demand (read+write) accesses
|
|
system.cpu2.icache.demand_avg_miss_latency 21650 # average overall miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency 18383.484163 # average overall mshr miss latency
|
|
system.cpu2.icache.demand_hits 22463 # number of demand (read+write) hits
|
|
system.cpu2.icache.demand_miss_latency 10608500 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.demand_miss_rate 0.021348 # miss rate for demand accesses
|
|
system.cpu2.icache.demand_misses 490 # number of demand (read+write) misses
|
|
system.cpu2.icache.demand_mshr_hits 48 # number of demand (read+write) MSHR hits
|
|
system.cpu2.icache.demand_mshr_miss_latency 8125500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_rate 0.019257 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.demand_mshr_misses 442 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.icache.occ_%::0 0.176697 # Average percentage of cache occupancy
|
|
system.cpu2.icache.occ_blocks::0 90.468971 # Average occupied blocks per context
|
|
system.cpu2.icache.overall_accesses 22953 # number of overall (read+write) accesses
|
|
system.cpu2.icache.overall_avg_miss_latency 21650 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency 18383.484163 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu2.icache.overall_hits 22463 # number of overall hits
|
|
system.cpu2.icache.overall_miss_latency 10608500 # number of overall miss cycles
|
|
system.cpu2.icache.overall_miss_rate 0.021348 # miss rate for overall accesses
|
|
system.cpu2.icache.overall_misses 490 # number of overall misses
|
|
system.cpu2.icache.overall_mshr_hits 48 # number of overall MSHR hits
|
|
system.cpu2.icache.overall_mshr_miss_latency 8125500 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_rate 0.019257 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.overall_mshr_misses 442 # number of overall MSHR misses
|
|
system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu2.icache.replacements 332 # number of replacements
|
|
system.cpu2.icache.sampled_refs 442 # Sample count of references to valid blocks.
|
|
system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu2.icache.tagsinuse 90.468971 # Cycle average of tags in use
|
|
system.cpu2.icache.total_refs 22463 # Total number of references to valid blocks.
|
|
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.icache.writebacks 0 # number of writebacks
|
|
system.cpu2.idleCycles 5817 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu2.iew.EXEC:branches 48053 # Number of branches executed
|
|
system.cpu2.iew.EXEC:nop 38997 # number of nop insts executed
|
|
system.cpu2.iew.EXEC:rate 1.144831 # Inst execution rate
|
|
system.cpu2.iew.EXEC:refs 111212 # number of memory reference insts executed
|
|
system.cpu2.iew.EXEC:stores 34898 # Number of stores executed
|
|
system.cpu2.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu2.iew.WB:consumers 131272 # num instructions consuming a value
|
|
system.cpu2.iew.WB:count 228549 # cumulative count of insts written-back
|
|
system.cpu2.iew.WB:fanout 0.972149 # average fanout of values written-back
|
|
system.cpu2.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu2.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu2.iew.WB:producers 127616 # num instructions producing a value
|
|
system.cpu2.iew.WB:rate 1.142991 # insts written-back per cycle
|
|
system.cpu2.iew.WB:sent 228678 # cumulative count of insts sent to commit
|
|
system.cpu2.iew.branchMispredicts 1190 # Number of branch mispredicts detected at execute
|
|
system.cpu2.iew.iewBlockCycles 1615 # Number of cycles IEW is blocking
|
|
system.cpu2.iew.iewDispLoadInsts 77014 # Number of dispatched load instructions
|
|
system.cpu2.iew.iewDispNonSpecInsts 921 # Number of dispatched non-speculative instructions
|
|
system.cpu2.iew.iewDispSquashedInsts 577 # Number of squashed instructions skipped by dispatch
|
|
system.cpu2.iew.iewDispStoreInsts 35289 # Number of dispatched store instructions
|
|
system.cpu2.iew.iewDispatchedInsts 271445 # Number of instructions dispatched to IQ
|
|
system.cpu2.iew.iewExecLoadInsts 76314 # Number of load instructions executed
|
|
system.cpu2.iew.iewExecSquashedInsts 958 # Number of squashed instructions skipped in execute
|
|
system.cpu2.iew.iewExecutedInsts 228917 # Number of executed instructions
|
|
system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall
|
|
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu2.iew.iewSquashCycles 1720 # Number of cycles IEW is squashing
|
|
system.cpu2.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking
|
|
system.cpu2.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu2.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu2.iew.lsq.thread.0.forwLoads 30681 # Number of loads that had data forwarded from stores
|
|
system.cpu2.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu2.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread.0.memOrderViolation 36 # Number of memory ordering violations
|
|
system.cpu2.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu2.iew.lsq.thread.0.squashedLoads 1419 # Number of loads squashed
|
|
system.cpu2.iew.lsq.thread.0.squashedStores 726 # Number of stores squashed
|
|
system.cpu2.iew.memOrderViolationEvents 36 # Number of memory order violations
|
|
system.cpu2.iew.predictedNotTakenIncorrect 197 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu2.iew.predictedTakenIncorrect 993 # Number of branches that were predicted taken incorrectly
|
|
system.cpu2.ipc 1.091475 # IPC: Instructions Per Cycle
|
|
system.cpu2.ipc_total 1.091475 # IPC: Total IPC of All Threads
|
|
system.cpu2.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::IntAlu 111470 48.49% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 48.49% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::MemRead 83479 36.31% 84.81% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::MemWrite 34926 15.19% 100.00% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.ISSUE:FU_type_0::total 229875 # Type of FU issued
|
|
system.cpu2.iq.ISSUE:fu_busy_cnt 190 # FU busy when requested
|
|
system.cpu2.iq.ISSUE:fu_busy_rate 0.000827 # FU busy rate (busy events/executed inst)
|
|
system.cpu2.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::IntAlu 11 5.79% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::IntMult 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.79% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::MemRead 48 25.26% 31.05% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::MemWrite 131 68.95% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::samples 194140 # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::mean 1.184068 # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::stdev 1.270828 # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::0 86894 44.76% 44.76% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::1 30647 15.79% 60.54% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::2 37182 19.15% 79.70% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::3 34986 18.02% 97.72% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::4 2607 1.34% 99.06% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::5 1569 0.81% 99.87% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::6 161 0.08% 99.95% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::7 85 0.04% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::8 9 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:issued_per_cycle::total 194140 # Number of insts issued each cycle
|
|
system.cpu2.iq.ISSUE:rate 1.149622 # Inst issue rate
|
|
system.cpu2.iq.iqInstsAdded 224210 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu2.iq.iqInstsIssued 229875 # Number of instructions issued
|
|
system.cpu2.iq.iqNonSpecInstsAdded 8238 # Number of non-speculative instructions added to the IQ
|
|
system.cpu2.iq.iqSquashedInstsExamined 6319 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu2.iq.iqSquashedNonSpecRemoved 541 # Number of squashed non-spec instructions that were removed
|
|
system.cpu2.iq.iqSquashedOperandsExamined 5841 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu2.memDep0.conflictingLoads 38126 # Number of conflicting loads.
|
|
system.cpu2.memDep0.conflictingStores 30815 # Number of conflicting stores.
|
|
system.cpu2.memDep0.insertedLoads 77014 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.insertedStores 35289 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu2.numCycles 199957 # number of cpu cycles simulated
|
|
system.cpu2.rename.RENAME:BlockCycles 8148 # Number of cycles rename is blocking
|
|
system.cpu2.rename.RENAME:CommittedMaps 179320 # Number of HB maps that are committed
|
|
system.cpu2.rename.RENAME:IQFullEvents 31 # Number of times rename has blocked due to IQ full
|
|
system.cpu2.rename.RENAME:IdleCycles 61271 # Number of cycles rename is idle
|
|
system.cpu2.rename.RENAME:LSQFullEvents 56 # Number of times rename has blocked due to LSQ full
|
|
system.cpu2.rename.RENAME:RenameLookups 515611 # Number of register rename lookups that rename has made
|
|
system.cpu2.rename.RENAME:RenamedInsts 273634 # Number of instructions processed by rename
|
|
system.cpu2.rename.RENAME:RenamedOperands 187411 # Number of destination operands rename has renamed
|
|
system.cpu2.rename.RENAME:RunCycles 102588 # Number of cycles rename is running
|
|
system.cpu2.rename.RENAME:SquashCycles 1720 # Number of cycles rename is squashing
|
|
system.cpu2.rename.RENAME:UnblockCycles 553 # Number of cycles rename is unblocking
|
|
system.cpu2.rename.RENAME:UndoneMaps 8091 # Number of HB maps that are undone due to squashing
|
|
system.cpu2.rename.RENAME:serializeStallCycles 13248 # count of cycles rename stalled for serializing inst
|
|
system.cpu2.rename.RENAME:serializingInsts 943 # count of serializing insts renamed
|
|
system.cpu2.rename.RENAME:skidInsts 2678 # count of insts added to the skid buffer
|
|
system.cpu2.rename.RENAME:tempSerializingInsts 998 # count of temporary serializing insts renamed
|
|
system.cpu2.timesIdled 306 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu3.BPredUnit.BTBHits 51008 # Number of BTB hits
|
|
system.cpu3.BPredUnit.BTBLookups 53230 # Number of BTB lookups
|
|
system.cpu3.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
|
system.cpu3.BPredUnit.condIncorrect 1107 # Number of conditional branches incorrect
|
|
system.cpu3.BPredUnit.condPredicted 53290 # Number of conditional branches predicted
|
|
system.cpu3.BPredUnit.lookups 53290 # Number of BP lookups
|
|
system.cpu3.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
|
system.cpu3.commit.COM:branches 50385 # Number of branches committed
|
|
system.cpu3.commit.COM:bw_lim_events 486 # number cycles where commit BW limit reached
|
|
system.cpu3.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu3.commit.COM:committed_per_cycle::samples 188101 # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::mean 1.497398 # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::stdev 1.921379 # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::0 83023 44.14% 44.14% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::1 51203 27.22% 71.36% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::2 7476 3.97% 75.33% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::3 8063 4.29% 79.62% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::4 2451 1.30% 80.92% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::5 34897 18.55% 99.47% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::6 373 0.20% 99.67% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::7 129 0.07% 99.74% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::8 486 0.26% 100.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:committed_per_cycle::total 188101 # Number of insts commited each cycle
|
|
system.cpu3.commit.COM:count 281662 # Number of instructions committed
|
|
system.cpu3.commit.COM:loads 81780 # Number of loads committed
|
|
system.cpu3.commit.COM:membars 6533 # Number of memory barriers committed
|
|
system.cpu3.commit.COM:refs 119669 # Number of memory references committed
|
|
system.cpu3.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu3.commit.branchMispredicts 1107 # The number of times a branch was mispredicted
|
|
system.cpu3.commit.commitCommittedInsts 281662 # The number of committed instructions
|
|
system.cpu3.commit.commitNonSpecStalls 7252 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu3.commit.commitSquashedInsts 8589 # The number of squashed insts skipped by commit
|
|
system.cpu3.committedInsts 233959 # Number of Instructions Simulated
|
|
system.cpu3.committedInsts_total 233959 # Number of Instructions Simulated
|
|
system.cpu3.cpi 0.853513 # CPI: Cycles Per Instruction
|
|
system.cpu3.cpi_total 0.853513 # CPI: Total CPI of All Threads
|
|
system.cpu3.dcache.ReadReq_accesses 48481 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency 22746.495327 # average ReadReq miss latency
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 14000 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.ReadReq_hits 48053 # number of ReadReq hits
|
|
system.cpu3.dcache.ReadReq_miss_latency 9735500 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.ReadReq_miss_rate 0.008828 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_misses 428 # number of ReadReq misses
|
|
system.cpu3.dcache.ReadReq_mshr_hits 266 # number of ReadReq MSHR hits
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency 2268000 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate 0.003342 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_mshr_misses 162 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_accesses 73 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency 25166.666667 # average SwapReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22166.666667 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_hits 13 # number of SwapReq hits
|
|
system.cpu3.dcache.SwapReq_miss_latency 1510000 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_rate 0.821918 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_misses 60 # number of SwapReq misses
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency 1330000 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate 0.821918 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_misses 60 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_accesses 37816 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency 24138.655462 # average WriteReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15764.705882 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_hits 37697 # number of WriteReq hits
|
|
system.cpu3.dcache.WriteReq_miss_latency 2872500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_rate 0.003147 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_misses 119 # number of WriteReq misses
|
|
system.cpu3.dcache.WriteReq_mshr_hits 17 # number of WriteReq MSHR hits
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency 1608000 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate 0.002697 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu3.dcache.avg_refs 1503.551724 # Average number of references to valid blocks.
|
|
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.dcache.demand_accesses 86297 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.demand_avg_miss_latency 23049.360146 # average overall miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency 14681.818182 # average overall mshr miss latency
|
|
system.cpu3.dcache.demand_hits 85750 # number of demand (read+write) hits
|
|
system.cpu3.dcache.demand_miss_latency 12608000 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.demand_miss_rate 0.006339 # miss rate for demand accesses
|
|
system.cpu3.dcache.demand_misses 547 # number of demand (read+write) misses
|
|
system.cpu3.dcache.demand_mshr_hits 283 # number of demand (read+write) MSHR hits
|
|
system.cpu3.dcache.demand_mshr_miss_latency 3876000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_rate 0.003059 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.demand_mshr_misses 264 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.dcache.occ_%::0 0.049235 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.occ_%::1 -0.015412 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.occ_blocks::0 25.208240 # Average occupied blocks per context
|
|
system.cpu3.dcache.occ_blocks::1 -7.890970 # Average occupied blocks per context
|
|
system.cpu3.dcache.overall_accesses 86297 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.overall_avg_miss_latency 23049.360146 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency 14681.818182 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu3.dcache.overall_hits 85750 # number of overall hits
|
|
system.cpu3.dcache.overall_miss_latency 12608000 # number of overall miss cycles
|
|
system.cpu3.dcache.overall_miss_rate 0.006339 # miss rate for overall accesses
|
|
system.cpu3.dcache.overall_misses 547 # number of overall misses
|
|
system.cpu3.dcache.overall_mshr_hits 283 # number of overall MSHR hits
|
|
system.cpu3.dcache.overall_mshr_miss_latency 3876000 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_rate 0.003059 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.overall_mshr_misses 264 # number of overall MSHR misses
|
|
system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu3.dcache.replacements 2 # number of replacements
|
|
system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks.
|
|
system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu3.dcache.tagsinuse 17.317269 # Cycle average of tags in use
|
|
system.cpu3.dcache.total_refs 43603 # Total number of references to valid blocks.
|
|
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.dcache.writebacks 1 # number of writebacks
|
|
system.cpu3.decode.DECODE:BlockedCycles 21721 # Number of cycles decode is blocked
|
|
system.cpu3.decode.DECODE:DecodedInsts 294320 # Number of instructions handled by decode
|
|
system.cpu3.decode.DECODE:IdleCycles 57795 # Number of cycles decode is idle
|
|
system.cpu3.decode.DECODE:RunCycles 102536 # Number of cycles decode is running
|
|
system.cpu3.decode.DECODE:SquashCycles 1822 # Number of cycles decode is squashing
|
|
system.cpu3.decode.DECODE:UnblockCycles 6048 # Number of cycles decode is unblocking
|
|
system.cpu3.fetch.Branches 53290 # Number of branches that fetch encountered
|
|
system.cpu3.fetch.CacheLines 21878 # Number of cache lines fetched
|
|
system.cpu3.fetch.Cycles 130861 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu3.fetch.IcacheSquashes 222 # Number of outstanding Icache misses that were squashed
|
|
system.cpu3.fetch.Insts 295471 # Number of instructions fetch has processed
|
|
system.cpu3.fetch.SquashCycles 1182 # Number of cycles fetch has spent squashing
|
|
system.cpu3.fetch.branchRate 0.266868 # Number of branch fetches per cycle
|
|
system.cpu3.fetch.icacheStallCycles 21878 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu3.fetch.predictedBranches 51008 # Number of branches that fetch has predicted taken
|
|
system.cpu3.fetch.rate 1.479671 # Number of inst fetches per cycle
|
|
system.cpu3.fetch.rateDist::samples 196540 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::mean 1.503363 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::stdev 2.005027 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::0 87581 44.56% 44.56% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::1 56529 28.76% 73.32% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::2 7663 3.90% 77.22% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::3 2862 1.46% 78.68% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::4 1914 0.97% 79.65% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::5 35780 18.20% 97.86% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::6 2478 1.26% 99.12% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::7 258 0.13% 99.25% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::8 1475 0.75% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::total 196540 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.icache.ReadReq_accesses 21878 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.ReadReq_avg_miss_latency 14319.791667 # average ReadReq miss latency
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11656.884876 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.ReadReq_hits 21398 # number of ReadReq hits
|
|
system.cpu3.icache.ReadReq_miss_latency 6873500 # number of ReadReq miss cycles
|
|
system.cpu3.icache.ReadReq_miss_rate 0.021940 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_misses 480 # number of ReadReq misses
|
|
system.cpu3.icache.ReadReq_mshr_hits 37 # number of ReadReq MSHR hits
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency 5164000 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate 0.020249 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_mshr_misses 443 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu3.icache.avg_refs 48.302483 # Average number of references to valid blocks.
|
|
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.icache.demand_accesses 21878 # number of demand (read+write) accesses
|
|
system.cpu3.icache.demand_avg_miss_latency 14319.791667 # average overall miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency 11656.884876 # average overall mshr miss latency
|
|
system.cpu3.icache.demand_hits 21398 # number of demand (read+write) hits
|
|
system.cpu3.icache.demand_miss_latency 6873500 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.demand_miss_rate 0.021940 # miss rate for demand accesses
|
|
system.cpu3.icache.demand_misses 480 # number of demand (read+write) misses
|
|
system.cpu3.icache.demand_mshr_hits 37 # number of demand (read+write) MSHR hits
|
|
system.cpu3.icache.demand_mshr_miss_latency 5164000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_rate 0.020249 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.demand_mshr_misses 443 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.icache.occ_%::0 0.172972 # Average percentage of cache occupancy
|
|
system.cpu3.icache.occ_blocks::0 88.561786 # Average occupied blocks per context
|
|
system.cpu3.icache.overall_accesses 21878 # number of overall (read+write) accesses
|
|
system.cpu3.icache.overall_avg_miss_latency 14319.791667 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency 11656.884876 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu3.icache.overall_hits 21398 # number of overall hits
|
|
system.cpu3.icache.overall_miss_latency 6873500 # number of overall miss cycles
|
|
system.cpu3.icache.overall_miss_rate 0.021940 # miss rate for overall accesses
|
|
system.cpu3.icache.overall_misses 480 # number of overall misses
|
|
system.cpu3.icache.overall_mshr_hits 37 # number of overall MSHR hits
|
|
system.cpu3.icache.overall_mshr_miss_latency 5164000 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_rate 0.020249 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.overall_mshr_misses 443 # number of overall MSHR misses
|
|
system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu3.icache.replacements 331 # number of replacements
|
|
system.cpu3.icache.sampled_refs 443 # Sample count of references to valid blocks.
|
|
system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu3.icache.tagsinuse 88.561786 # Cycle average of tags in use
|
|
system.cpu3.icache.total_refs 21398 # Total number of references to valid blocks.
|
|
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.icache.writebacks 0 # number of writebacks
|
|
system.cpu3.idleCycles 3147 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu3.iew.EXEC:branches 50939 # Number of branches executed
|
|
system.cpu3.iew.EXEC:nop 42047 # number of nop insts executed
|
|
system.cpu3.iew.EXEC:rate 1.222869 # Inst execution rate
|
|
system.cpu3.iew.EXEC:refs 120748 # number of memory reference insts executed
|
|
system.cpu3.iew.EXEC:stores 38237 # Number of stores executed
|
|
system.cpu3.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu3.iew.WB:consumers 140792 # num instructions consuming a value
|
|
system.cpu3.iew.WB:count 243825 # cumulative count of insts written-back
|
|
system.cpu3.iew.WB:fanout 0.974075 # average fanout of values written-back
|
|
system.cpu3.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu3.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu3.iew.WB:producers 137142 # num instructions producing a value
|
|
system.cpu3.iew.WB:rate 1.221036 # insts written-back per cycle
|
|
system.cpu3.iew.WB:sent 243958 # cumulative count of insts sent to commit
|
|
system.cpu3.iew.branchMispredicts 1214 # Number of branch mispredicts detected at execute
|
|
system.cpu3.iew.iewBlockCycles 1672 # Number of cycles IEW is blocking
|
|
system.cpu3.iew.iewDispLoadInsts 83367 # Number of dispatched load instructions
|
|
system.cpu3.iew.iewDispNonSpecInsts 943 # Number of dispatched non-speculative instructions
|
|
system.cpu3.iew.iewDispSquashedInsts 577 # Number of squashed instructions skipped by dispatch
|
|
system.cpu3.iew.iewDispStoreInsts 38663 # Number of dispatched store instructions
|
|
system.cpu3.iew.iewDispatchedInsts 290280 # Number of instructions dispatched to IQ
|
|
system.cpu3.iew.iewExecLoadInsts 82511 # Number of load instructions executed
|
|
system.cpu3.iew.iewExecSquashedInsts 965 # Number of squashed instructions skipped in execute
|
|
system.cpu3.iew.iewExecutedInsts 244191 # Number of executed instructions
|
|
system.cpu3.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall
|
|
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu3.iew.iewSquashCycles 1822 # Number of cycles IEW is squashing
|
|
system.cpu3.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking
|
|
system.cpu3.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu3.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu3.iew.lsq.thread.0.forwLoads 34012 # Number of loads that had data forwarded from stores
|
|
system.cpu3.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu3.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu3.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu3.iew.lsq.thread.0.memOrderViolation 33 # Number of memory ordering violations
|
|
system.cpu3.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu3.iew.lsq.thread.0.squashedLoads 1587 # Number of loads squashed
|
|
system.cpu3.iew.lsq.thread.0.squashedStores 774 # Number of stores squashed
|
|
system.cpu3.iew.memOrderViolationEvents 33 # Number of memory order violations
|
|
system.cpu3.iew.predictedNotTakenIncorrect 191 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu3.iew.predictedTakenIncorrect 1023 # Number of branches that were predicted taken incorrectly
|
|
system.cpu3.ipc 1.171629 # IPC: Instructions Per Cycle
|
|
system.cpu3.ipc_total 1.171629 # IPC: Total IPC of All Threads
|
|
system.cpu3.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::IntAlu 117660 47.99% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 47.99% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::MemRead 89228 36.40% 84.39% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::MemWrite 38268 15.61% 100.00% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu3.iq.ISSUE:FU_type_0::total 245156 # Type of FU issued
|
|
system.cpu3.iq.ISSUE:fu_busy_cnt 195 # FU busy when requested
|
|
system.cpu3.iq.ISSUE:fu_busy_rate 0.000795 # FU busy rate (busy events/executed inst)
|
|
system.cpu3.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::IntAlu 10 5.13% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::IntMult 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.13% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::MemRead 54 27.69% 32.82% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::MemWrite 131 67.18% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::samples 196540 # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::mean 1.247359 # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::stdev 1.278033 # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::0 83952 42.71% 42.71% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::1 29215 14.86% 57.58% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::2 40646 20.68% 78.26% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::3 38400 19.54% 97.80% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::4 2533 1.29% 99.09% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::5 1549 0.79% 99.88% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::6 153 0.08% 99.95% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::7 82 0.04% 99.99% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::8 10 0.01% 100.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:issued_per_cycle::total 196540 # Number of insts issued each cycle
|
|
system.cpu3.iq.ISSUE:rate 1.227701 # Inst issue rate
|
|
system.cpu3.iq.iqInstsAdded 240287 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu3.iq.iqInstsIssued 245156 # Number of instructions issued
|
|
system.cpu3.iq.iqNonSpecInstsAdded 7946 # Number of non-speculative instructions added to the IQ
|
|
system.cpu3.iq.iqSquashedInstsExamined 6812 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu3.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
|
|
system.cpu3.iq.iqSquashedNonSpecRemoved 694 # Number of squashed non-spec instructions that were removed
|
|
system.cpu3.iq.iqSquashedOperandsExamined 6560 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu3.memDep0.conflictingLoads 41143 # Number of conflicting loads.
|
|
system.cpu3.memDep0.conflictingStores 34165 # Number of conflicting stores.
|
|
system.cpu3.memDep0.insertedLoads 83367 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu3.memDep0.insertedStores 38663 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu3.numCycles 199687 # number of cpu cycles simulated
|
|
system.cpu3.rename.RENAME:BlockCycles 7785 # Number of cycles rename is blocking
|
|
system.cpu3.rename.RENAME:CommittedMaps 192153 # Number of HB maps that are committed
|
|
system.cpu3.rename.RENAME:IQFullEvents 59 # Number of times rename has blocked due to IQ full
|
|
system.cpu3.rename.RENAME:IdleCycles 58421 # Number of cycles rename is idle
|
|
system.cpu3.rename.RENAME:LSQFullEvents 39 # Number of times rename has blocked due to LSQ full
|
|
system.cpu3.rename.RENAME:RenameLookups 554540 # Number of register rename lookups that rename has made
|
|
system.cpu3.rename.RENAME:RenamedInsts 292537 # Number of instructions processed by rename
|
|
system.cpu3.rename.RENAME:RenamedOperands 200475 # Number of destination operands rename has renamed
|
|
system.cpu3.rename.RENAME:RunCycles 108103 # Number of cycles rename is running
|
|
system.cpu3.rename.RENAME:SquashCycles 1822 # Number of cycles rename is squashing
|
|
system.cpu3.rename.RENAME:UnblockCycles 588 # Number of cycles rename is unblocking
|
|
system.cpu3.rename.RENAME:UndoneMaps 8322 # Number of HB maps that are undone due to squashing
|
|
system.cpu3.rename.RENAME:serializeStallCycles 13203 # count of cycles rename stalled for serializing inst
|
|
system.cpu3.rename.RENAME:serializingInsts 964 # count of serializing insts renamed
|
|
system.cpu3.rename.RENAME:skidInsts 2784 # count of insts added to the skid buffer
|
|
system.cpu3.rename.RENAME:tempSerializingInsts 1016 # count of temporary serializing insts renamed
|
|
system.cpu3.timesIdled 292 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.l2c.ReadExReq_accesses::0 94 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::2 13 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_avg_miss_latency::0 73159.574468 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::1 573083.333333 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::2 529000 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::3 573083.333333 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 1748326.241135 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 40290.076336 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_miss_latency 6877000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_misses::0 94 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::2 13 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_mshr_miss_latency 5278000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_rate::0 1.393617 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::2 10.076923 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_misses 131 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadReq_accesses::0 689 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::1 459 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::2 456 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::3 456 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 2060 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_avg_miss_latency::0 63648.106904 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::1 2381500 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::2 340214.285714 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::3 5715600 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 8500962.392619 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 40001.841621 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_hits::0 240 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::1 447 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::2 372 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::3 451 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1510 # number of ReadReq hits
|
|
system.l2c.ReadReq_miss_latency 28578000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_rate::0 0.651669 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::1 0.026144 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::2 0.184211 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::3 0.010965 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.872988 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_misses::0 449 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::1 12 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::2 84 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::3 5 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 550 # number of ReadReq misses
|
|
system.l2c.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_miss_latency 21721000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::0 0.788099 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::1 1.183007 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::2 1.190789 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::3 1.190789 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 4.352684 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_misses 543 # number of ReadReq MSHR misses
|
|
system.l2c.UpgradeReq_accesses::0 29 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::1 21 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::2 25 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::3 23 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 98 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_avg_miss_latency::0 6000 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::1 7428.571429 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::2 6240 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::3 6782.608696 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 26451.180124 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_hits::0 3 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_miss_latency 156000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_rate::0 0.896552 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 3.896552 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_misses::0 26 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::1 21 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::2 25 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::3 23 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 95 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency 3800000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_rate::0 3.275862 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::1 4.523810 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::2 3.800000 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::3 4.130435 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 15.730106 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_misses 95 # number of UpgradeReq MSHR misses
|
|
system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_hits::0 9 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 9 # number of Writeback hits
|
|
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.l2c.avg_refs 2.765138 # Average number of references to valid blocks.
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.demand_accesses::0 783 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::1 471 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::2 469 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::3 468 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2191 # number of demand (read+write) accesses
|
|
system.l2c.demand_avg_miss_latency::0 65294.659300 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::1 1477291.666667 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::2 365515.463918 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::3 2085588.235294 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 3993690.025178 # average overall miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency 40057.863501 # average overall mshr miss latency
|
|
system.l2c.demand_hits::0 240 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::1 447 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::2 372 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::3 451 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1510 # number of demand (read+write) hits
|
|
system.l2c.demand_miss_latency 35455000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_rate::0 0.693487 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::1 0.050955 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::2 0.206823 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::3 0.036325 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.987590 # miss rate for demand accesses
|
|
system.l2c.demand_misses::0 543 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::1 24 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::2 97 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::3 17 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 681 # number of demand (read+write) misses
|
|
system.l2c.demand_mshr_hits 7 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_miss_latency 26999000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_rate::0 0.860792 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::1 1.430998 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::2 1.437100 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::3 1.440171 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 5.169061 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_misses 674 # number of demand (read+write) MSHR misses
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.occ_%::0 0.005562 # Average percentage of cache occupancy
|
|
system.l2c.occ_%::1 0.000141 # Average percentage of cache occupancy
|
|
system.l2c.occ_%::2 0.000962 # Average percentage of cache occupancy
|
|
system.l2c.occ_%::3 0.000050 # Average percentage of cache occupancy
|
|
system.l2c.occ_%::4 0.000078 # Average percentage of cache occupancy
|
|
system.l2c.occ_blocks::0 364.482094 # Average occupied blocks per context
|
|
system.l2c.occ_blocks::1 9.273148 # Average occupied blocks per context
|
|
system.l2c.occ_blocks::2 63.060647 # Average occupied blocks per context
|
|
system.l2c.occ_blocks::3 3.262767 # Average occupied blocks per context
|
|
system.l2c.occ_blocks::4 5.106132 # Average occupied blocks per context
|
|
system.l2c.overall_accesses::0 783 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::1 471 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::2 469 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::3 468 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2191 # number of overall (read+write) accesses
|
|
system.l2c.overall_avg_miss_latency::0 65294.659300 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::1 1477291.666667 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::2 365515.463918 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::3 2085588.235294 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 3993690.025178 # average overall miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency 40057.863501 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.l2c.overall_hits::0 240 # number of overall hits
|
|
system.l2c.overall_hits::1 447 # number of overall hits
|
|
system.l2c.overall_hits::2 372 # number of overall hits
|
|
system.l2c.overall_hits::3 451 # number of overall hits
|
|
system.l2c.overall_hits::total 1510 # number of overall hits
|
|
system.l2c.overall_miss_latency 35455000 # number of overall miss cycles
|
|
system.l2c.overall_miss_rate::0 0.693487 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::1 0.050955 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::2 0.206823 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::3 0.036325 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.987590 # miss rate for overall accesses
|
|
system.l2c.overall_misses::0 543 # number of overall misses
|
|
system.l2c.overall_misses::1 24 # number of overall misses
|
|
system.l2c.overall_misses::2 97 # number of overall misses
|
|
system.l2c.overall_misses::3 17 # number of overall misses
|
|
system.l2c.overall_misses::total 681 # number of overall misses
|
|
system.l2c.overall_mshr_hits 7 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_miss_latency 26999000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_rate::0 0.860792 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::1 1.430998 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::2 1.437100 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::3 1.440171 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 5.169061 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_misses 674 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.l2c.replacements 0 # number of replacements
|
|
system.l2c.sampled_refs 545 # Sample count of references to valid blocks.
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.l2c.tagsinuse 445.184788 # Cycle average of tags in use
|
|
system.l2c.total_refs 1507 # Total number of references to valid blocks.
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.writebacks 0 # number of writebacks
|
|
|
|
---------- End Simulation Statistics ----------
|