741 lines
83 KiB
Plaintext
741 lines
83 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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host_inst_rate 36918 # Simulator instruction rate (inst/s)
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host_mem_usage 190384 # Number of bytes of host memory used
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host_seconds 0.35 # Real time elapsed on the host
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host_tick_rate 41160042 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 12773 # Number of instructions simulated
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sim_seconds 0.000014 # Number of seconds simulated
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sim_ticks 14251500 # Number of ticks simulated
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.BTBHits 916 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 4733 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 1595 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 3153 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 5548 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 681 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches::0 1051 # Number of branches committed
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system.cpu.commit.COM:branches::1 1051 # Number of branches committed
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system.cpu.commit.COM:branches::total 2102 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 122 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited::0 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:bw_limited::1 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:bw_limited::total 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle::samples 22838 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 0.560776 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 1.272228 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0-1 16881 73.92% 73.92% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1-2 3016 13.21% 87.12% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2-3 1386 6.07% 93.19% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3-4 576 2.52% 95.71% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4-5 326 1.43% 97.14% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5-6 268 1.17% 98.31% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6-7 170 0.74% 99.06% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7-8 93 0.41% 99.47% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 122 0.53% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::total 22838 # Number of insts commited each cycle
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system.cpu.commit.COM:count::0 6403 # Number of instructions committed
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system.cpu.commit.COM:count::1 6404 # Number of instructions committed
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system.cpu.commit.COM:count::total 12807 # Number of instructions committed
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system.cpu.commit.COM:loads::0 1185 # Number of loads committed
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system.cpu.commit.COM:loads::1 1185 # Number of loads committed
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system.cpu.commit.COM:loads::total 2370 # Number of loads committed
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system.cpu.commit.COM:membars::0 0 # Number of memory barriers committed
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system.cpu.commit.COM:membars::1 0 # Number of memory barriers committed
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system.cpu.commit.COM:membars::total 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs::0 2050 # Number of memory references committed
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system.cpu.commit.COM:refs::1 2050 # Number of memory references committed
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system.cpu.commit.COM:refs::total 4100 # Number of memory references committed
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system.cpu.commit.COM:swp_count::0 0 # Number of s/w prefetches committed
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system.cpu.commit.COM:swp_count::1 0 # Number of s/w prefetches committed
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system.cpu.commit.COM:swp_count::total 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 1166 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 10895 # The number of squashed insts skipped by commit
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system.cpu.committedInsts::0 6386 # Number of Instructions Simulated
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system.cpu.committedInsts::1 6387 # Number of Instructions Simulated
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system.cpu.committedInsts_total 12773 # Number of Instructions Simulated
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system.cpu.cpi::0 4.463514 # CPI: Cycles Per Instruction
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system.cpu.cpi::1 4.462815 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 2.231582 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses::0 3925 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 3925 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency::0 35473.913043 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36849.514563 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits::0 3580 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 3580 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency::0 12238500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 12238500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate::0 0.087898 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses::0 345 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 345 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits::0 139 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_hits::total 139 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency::0 7591000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 7591000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.052484 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses::0 206 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_misses::total 206 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses::0 1730 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency::0 33703.947368 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36103.448276 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits::0 970 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 970 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency::0 25615000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 25615000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate::0 0.439306 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses::0 760 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 760 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits::0 586 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits::total 586 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency::0 6282000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 6282000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.100578 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses::0 174 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 174 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 13.102273 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses::0 5655 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 5655 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency::0 34256.561086 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::0 36507.894737 # average overall mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
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system.cpu.dcache.demand_hits::0 4550 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 4550 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency::0 37853500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 37853500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate::0 0.195402 # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
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system.cpu.dcache.demand_misses::0 1105 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 1105 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits::0 725 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_hits::total 725 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency::0 13873000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 13873000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate::0 0.067197 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses::0 380 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 380 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events::0 0 # number of times MSHR cap was activated
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system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated
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system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses::0 5655 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 5655 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency::0 34256.561086 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::0 36507.894737 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits::0 4550 # number of overall hits
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system.cpu.dcache.overall_hits::1 0 # number of overall hits
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system.cpu.dcache.overall_hits::total 4550 # number of overall hits
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system.cpu.dcache.overall_miss_latency::0 37853500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 37853500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate::0 0.195402 # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
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system.cpu.dcache.overall_misses::0 1105 # number of overall misses
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system.cpu.dcache.overall_misses::1 0 # number of overall misses
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system.cpu.dcache.overall_misses::total 1105 # number of overall misses
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system.cpu.dcache.overall_mshr_hits::0 725 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 725 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency::0 13873000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 13873000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate::0 0.067197 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses::0 380 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 380 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements::0 0 # number of replacements
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system.cpu.dcache.replacements::1 0 # number of replacements
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system.cpu.dcache.replacements::total 0 # number of replacements
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system.cpu.dcache.sampled_refs 352 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 223.700041 # Cycle average of tags in use
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system.cpu.dcache.total_refs 4612 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks::0 0 # number of writebacks
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system.cpu.dcache.writebacks::1 0 # number of writebacks
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system.cpu.dcache.writebacks::total 0 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 5063 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 441 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 602 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 27492 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 33392 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 4878 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 2128 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 668 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 186 # Number of cycles decode is unblocking
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system.cpu.dtb.data_accesses 6300 # DTB accesses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_hits 6155 # DTB hits
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system.cpu.dtb.data_misses 145 # DTB misses
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.read_accesses 4144 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 4056 # DTB read hits
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system.cpu.dtb.read_misses 88 # DTB read misses
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system.cpu.dtb.write_accesses 2156 # DTB write accesses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_hits 2099 # DTB write hits
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system.cpu.dtb.write_misses 57 # DTB write misses
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system.cpu.fetch.Branches 5548 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 4113 # Number of cache lines fetched
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system.cpu.fetch.Cycles 9444 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 613 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 30949 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 1712 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.194639 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 4113 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 1597 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.085777 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist::samples 22904 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.351249 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.742840 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0-1 17622 76.94% 76.94% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1-2 416 1.82% 78.75% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2-3 353 1.54% 80.30% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3-4 477 2.08% 82.38% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4-5 425 1.86% 84.23% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5-6 349 1.52% 85.76% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6-7 442 1.93% 87.69% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7-8 261 1.14% 88.83% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 2559 11.17% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 22904 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.icache.ReadReq_accesses::0 4113 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 4113 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_avg_miss_latency::0 35793.697979 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35516.155089 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_hits::0 3272 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 3272 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_miss_latency::0 30102500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 30102500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_rate::0 0.204474 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_misses::0 841 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 841 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_mshr_hits::0 222 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 222 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::0 21984500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 21984500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.150498 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_misses::0 619 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 619 # number of ReadReq MSHR misses
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_refs 5.285945 # Average number of references to valid blocks.
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.demand_accesses::0 4113 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 4113 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_avg_miss_latency::0 35793.697979 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::0 35516.155089 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
|
|
system.cpu.icache.demand_hits::0 3272 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 3272 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_miss_latency::0 30102500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 30102500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_rate::0 0.204474 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.cpu.icache.demand_misses::0 841 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 841 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_mshr_hits::0 222 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 222 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_miss_latency::0 21984500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 21984500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_rate::0 0.150498 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_misses::0 619 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 619 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.mshr_cap_events::0 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.overall_accesses::0 4113 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 4113 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_avg_miss_latency::0 35793.697979 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::0 35516.155089 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_hits::0 3272 # number of overall hits
|
|
system.cpu.icache.overall_hits::1 0 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 3272 # number of overall hits
|
|
system.cpu.icache.overall_miss_latency::0 30102500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 30102500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_rate::0 0.204474 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.cpu.icache.overall_misses::0 841 # number of overall misses
|
|
system.cpu.icache.overall_misses::1 0 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 841 # number of overall misses
|
|
system.cpu.icache.overall_mshr_hits::0 222 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 222 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_miss_latency::0 21984500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 21984500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_rate::0 0.150498 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_misses::0 619 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 619 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.replacements::0 6 # number of replacements
|
|
system.cpu.icache.replacements::1 0 # number of replacements
|
|
system.cpu.icache.replacements::total 6 # number of replacements
|
|
system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks.
|
|
system.cpu.icache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.tagsinuse 321.284131 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 3272 # Total number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.writebacks::0 0 # number of writebacks
|
|
system.cpu.icache.writebacks::1 0 # number of writebacks
|
|
system.cpu.icache.writebacks::total 0 # number of writebacks
|
|
system.cpu.idleCycles 5600 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.iew.EXEC:branches::0 1573 # Number of branches executed
|
|
system.cpu.iew.EXEC:branches::1 1587 # Number of branches executed
|
|
system.cpu.iew.EXEC:branches::total 3160 # Number of branches executed
|
|
system.cpu.iew.EXEC:nop::0 70 # number of nop insts executed
|
|
system.cpu.iew.EXEC:nop::1 65 # number of nop insts executed
|
|
system.cpu.iew.EXEC:nop::total 135 # number of nop insts executed
|
|
system.cpu.iew.EXEC:rate 0.673940 # Inst execution rate
|
|
system.cpu.iew.EXEC:refs::0 3132 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:refs::1 3189 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:refs::total 6321 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:stores::0 1090 # Number of stores executed
|
|
system.cpu.iew.EXEC:stores::1 1085 # Number of stores executed
|
|
system.cpu.iew.EXEC:stores::total 2175 # Number of stores executed
|
|
system.cpu.iew.EXEC:swp::0 0 # number of swp insts executed
|
|
system.cpu.iew.EXEC:swp::1 0 # number of swp insts executed
|
|
system.cpu.iew.EXEC:swp::total 0 # number of swp insts executed
|
|
system.cpu.iew.WB:consumers::0 5984 # num instructions consuming a value
|
|
system.cpu.iew.WB:consumers::1 5917 # num instructions consuming a value
|
|
system.cpu.iew.WB:consumers::total 11901 # num instructions consuming a value
|
|
system.cpu.iew.WB:count::0 9221 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:count::1 9205 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:count::total 18426 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:fanout::0 0.776404 # average fanout of values written-back
|
|
system.cpu.iew.WB:fanout::1 0.776407 # average fanout of values written-back
|
|
system.cpu.iew.WB:fanout::total 1.552811 # average fanout of values written-back
|
|
system.cpu.iew.WB:penalized::0 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized::1 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized::total 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:producers::0 4646 # num instructions producing a value
|
|
system.cpu.iew.WB:producers::1 4594 # num instructions producing a value
|
|
system.cpu.iew.WB:producers::total 9240 # num instructions producing a value
|
|
system.cpu.iew.WB:rate::0 0.323498 # insts written-back per cycle
|
|
system.cpu.iew.WB:rate::1 0.322937 # insts written-back per cycle
|
|
system.cpu.iew.WB:rate::total 0.646436 # insts written-back per cycle
|
|
system.cpu.iew.WB:sent::0 9324 # cumulative count of insts sent to commit
|
|
system.cpu.iew.WB:sent::1 9340 # cumulative count of insts sent to commit
|
|
system.cpu.iew.WB:sent::total 18664 # cumulative count of insts sent to commit
|
|
system.cpu.iew.branchMispredicts 1342 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewBlockCycles 1080 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewDispLoadInsts 4951 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewDispSquashedInsts 727 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispStoreInsts 2585 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispatchedInsts 23775 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewExecLoadInsts::0 2042 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts::1 2104 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts::total 4146 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1180 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.iewExecutedInsts 19210 # Number of executed instructions
|
|
system.cpu.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 2128 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 1246 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 417 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.1.forwLoads 72 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.1.memOrderViolation 68 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.1.squashedLoads 1335 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.1.squashedStores 438 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 136 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 1080 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 262 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc::0 0.224039 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc::1 0.224074 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.448113 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 6830 67.10% 67.12% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.13% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.13% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.15% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.15% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.15% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.15% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.15% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.15% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 2173 21.35% 88.50% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1171 11.50% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::total 10179 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::IntAlu 6842 67.01% 67.03% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::IntMult 1 0.01% 67.04% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::IntDiv 0 0.00% 67.04% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::FloatAdd 2 0.02% 67.06% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::FloatCmp 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::FloatCvt 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::FloatMult 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::FloatDiv 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::FloatSqrt 0 0.00% 67.06% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::MemRead 2230 21.84% 88.89% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::MemWrite 1134 11.11% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1::total 10211 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::IntAlu 13672 67.05% 67.07% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::IntMult 2 0.01% 67.08% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::IntDiv 0 0.00% 67.08% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::FloatAdd 4 0.02% 67.10% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::FloatCmp 0 0.00% 67.10% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::FloatCvt 0 0.00% 67.10% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::FloatMult 0 0.00% 67.10% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::FloatDiv 0 0.00% 67.10% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::FloatSqrt 0 0.00% 67.10% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::MemRead 4403 21.59% 88.70% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::MemWrite 2305 11.30% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type::total 20390 # Type of FU issued
|
|
system.cpu.iq.ISSUE:fu_busy_cnt::0 87 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_cnt::1 85 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_cnt::total 172 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate::0 0.004267 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_busy_rate::1 0.004169 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_busy_rate::total 0.008436 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 13 7.56% 7.56% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 7.56% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.56% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.56% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.56% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.56% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.56% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.56% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.56% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 96 55.81% 63.37% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 63 36.63% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 22904 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.890238 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.446450 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0-1 14156 61.81% 61.81% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1-2 3289 14.36% 76.17% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2-3 2351 10.26% 86.43% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3-4 1373 5.99% 92.42% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4-5 854 3.73% 96.15% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5-6 535 2.34% 98.49% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6-7 261 1.14% 99.63% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7-8 57 0.25% 99.88% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 28 0.12% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 22904 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:rate 0.715338 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 23596 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 20390 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 9662 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 5422 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.fetch_accesses 4162 # ITB accesses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_hits 4113 # ITB hits
|
|
system.cpu.itb.fetch_misses 49 # ITB misses
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.l2cache.ReadExReq_accesses::0 146 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34643.835616 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31589.041096 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_miss_latency::0 5058000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 5058000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses::0 146 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4612000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4612000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses::0 825 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 825 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::0 34555.285541 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31414.337789 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits::0 2 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency::0 28439000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 28439000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate::0 0.997576 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses::0 823 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 823 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25854000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25854000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997576 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::0 823 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 823 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_accesses::0 28 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 28 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::0 34482.142857 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::0 31357.142857 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::0 965500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 965500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_misses::0 28 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 28 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::0 878000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 878000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::0 28 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 28 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6750 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 0.002516 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 27000 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses::0 971 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 971 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency::0 34568.627451 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::1 no_value # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total no_value # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31440.660475 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits::0 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency::0 33497000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 33497000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate::0 0.997940 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses::0 969 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 969 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency::0 30466000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 30466000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate::0 0.997940 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses::0 969 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 969 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses::0 971 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 971 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency::0 34568.627451 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::1 no_value # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total no_value # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31440.660475 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits::0 2 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::1 0 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency::0 33497000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 33497000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate::0 0.997940 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses::0 969 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::1 0 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 969 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency::0 30466000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 30466000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate::0 0.997940 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses::0 969 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 969 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.replacements::0 0 # number of replacements
|
|
system.cpu.l2cache.replacements::1 0 # number of replacements
|
|
system.cpu.l2cache.replacements::total 0 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 795 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 435.713880 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks::0 0 # number of writebacks
|
|
system.cpu.l2cache.writebacks::1 0 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 0 # number of writebacks
|
|
system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores.
|
|
system.cpu.memDep0.insertedLoads 2431 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 1282 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep1.conflictingLoads 58 # Number of conflicting loads.
|
|
system.cpu.memDep1.conflictingStores 32 # Number of conflicting stores.
|
|
system.cpu.memDep1.insertedLoads 2520 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep1.insertedStores 1303 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.numCycles 28504 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 2835 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IdleCycles 33866 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 1399 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.RENAME:RenameLookups 32685 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 26128 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 19538 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 4546 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 2128 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 1422 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 10372 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 850 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 3399 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls
|
|
system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|