gem5/arch/alpha/isa
Steve Reinhardt 3923eec0ef Change how memory operands are handled in ISA descriptions.
Should enable implementation of split-phase timing loads
with new memory model.
May create slight timing differences under FullCPU, as I
believe we were not handling software prefetches correctly
before when the split MemAcc/Exec model was used.  I haven't
looked into this in any detail though.

arch/alpha/isa/decoder.isa:
    HwLoadStore format split into separate HwLoad and
    HwStore formats.
    Copy instructions now fall under MiscPrefetch format.
    Mem_write_result is now just write_result in store
    conditionals.
arch/alpha/isa/mem.isa:
    Split MemAccExecute and LoadStoreExecute templates
    into separate templates for loads and stores; now
    that memory operands are handled differently from
    registers, it's impossible to have a single template
    serve both.
    Also unified the handling of "regular" prefetches
    (loads to r31) and "misc" prefetches (e.g., wh64)
    under the new scheme.  It looks like SW prefetches
    were not handled correctly in FullCPU up til now,
    since we generated an execute() method for the outer
    instruction but didn't generate a proper method for
    MemAcc::execute() (instead getting a default no-op
    method for that).
arch/alpha/isa/pal.isa:
    Split HwLoadStore into separate HwLoad and HwStore
    formats to select proper template (see change to
    mem.isa in this changeset).
arch/isa_parser.py:
    Stop trying to treat memory operands like register
    operands, since we never used them in a uniform way
    anyway, and it made it impossible to do split-phase
    loads as needed for the new CPU model.  Now there's no
    more 'op_mem_rd', 'op_nonmem_rd', etc.: 'op_rd' just does
    register operands, and the template code is responsible
    for formulating the call to the memory system.  Right now
    the only thing exported by InstObjParams is a new attribute
    'mem_acc_size' which gives the memory access size in bits,
    though more attributes can be added if needed.

    Also moved code in findOperands() method to
    OperandDescriptorList.__init__(), which is where it belongs.

--HG--
extra : convert_revision : 6d53d07e0c5e828455834ded4395fa40f9146a34
2006-02-10 09:12:55 -05:00
..
branch.isa Split Alpha ISA description into multiple files 2006-02-09 23:02:38 -05:00
decoder.isa Change how memory operands are handled in ISA descriptions. 2006-02-10 09:12:55 -05:00
fp.isa Split Alpha ISA description into multiple files 2006-02-09 23:02:38 -05:00
int.isa Split Alpha ISA description into multiple files 2006-02-09 23:02:38 -05:00
main.isa Split Alpha ISA description into multiple files 2006-02-09 23:02:38 -05:00
mem.isa Change how memory operands are handled in ISA descriptions. 2006-02-10 09:12:55 -05:00
pal.isa Change how memory operands are handled in ISA descriptions. 2006-02-10 09:12:55 -05:00
unimp.isa Split Alpha ISA description into multiple files 2006-02-09 23:02:38 -05:00
unknown.isa Split Alpha ISA description into multiple files 2006-02-09 23:02:38 -05:00
util.isa Split Alpha ISA description into multiple files 2006-02-09 23:02:38 -05:00