13f8dc981f
ticks for the most commonly accessed devices.
dev/baddev.cc:
Get rid of the constant cache access latency.
For unimportant devices, don't add any latency.
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart.cc:
dev/uart.hh:
make the cache access latency a parameter that is based on bus
ticks.
dev/io_device.cc:
dev/io_device.hh:
add an io latency variable
dev/ns_gige.hh:
this moved to io_device.hh
--HG--
extra : convert_revision : 4883130feeaef48abee492eddf0b8eb40eb94789
131 lines
4.3 KiB
C++
131 lines
4.3 KiB
C++
/*
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* Copyright (c) 2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* Tsunami PChip
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*/
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#ifndef __TSUNAMI_PCHIP_HH__
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#define __TSUNAMI_PCHIP_HH__
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#include "dev/tsunami.hh"
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#include "base/range.hh"
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#include "dev/io_device.hh"
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/*
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* Tsunami PChip
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*/
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class TsunamiPChip : public PioDevice
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{
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private:
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/** The base address of this device */
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Addr addr;
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/** The size of mappad from the above address */
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static const Addr size = 0xfff;
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protected:
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/**
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* pointer to the tsunami object.
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* This is our access to all the other tsunami
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* devices.
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*/
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Tsunami *tsunami;
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/** Pchip control register */
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uint64_t pctl;
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/** Window Base addresses */
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uint64_t wsba[4];
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/** Window masks */
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uint64_t wsm[4];
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/** Translated Base Addresses */
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uint64_t tba[4];
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public:
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/**
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* Register the PChip with the mmu and init all wsba, wsm, and tba to 0
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* @param name the name of thes device
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* @param t a pointer to the tsunami device
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* @param a the address which we respond to
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* @param mmu the mmu we are to register with
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* @param hier object to store parameters universal the device hierarchy
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* @param bus The bus that this device is attached to
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*/
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TsunamiPChip(const std::string &name, Tsunami *t, Addr a,
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MemoryController *mmu, HierParams *hier, Bus *bus,
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Tick pio_latency);
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/**
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* Translate a PCI bus address to a memory address for DMA.
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* @todo Andrew says this needs to be fixed. What's wrong with it?
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* @param busAddr PCI address to translate.
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* @return memory system address
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*/
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Addr translatePciToDma(Addr busAddr);
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/**
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* Process a read to the PChip.
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* @param req Contains the address to read from.
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* @param data A pointer to write the read data to.
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* @return The fault condition of the access.
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*/
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virtual Fault read(MemReqPtr &req, uint8_t *data);
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/**
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* Process a write to the PChip.
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* @param req Contains the address to write to.
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* @param data The data to write.
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* @return The fault condition of the access.
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*/
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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virtual void serialize(std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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/**
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* Return how long this access will take.
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* @param req the memory request to calcuate
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* @return Tick when the request is done
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*/
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Tick cacheAccess(MemReqPtr &req);
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};
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#endif // __TSUNAMI_PCHIP_HH__
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