a183f66a8a
Have FP conversion instructions use re-defined convert_and_round() function
arch/mips/isa/decoder.isa:
Use lower two bits of FCSR reg to determine rounding mode (may want to move this out of decoder.isa and into a template)
Have FP conversion instructions to use re-defined convert_and_round() function
arch/mips/isa/formats/util.isa:
Remove convert_and_round function from here
arch/mips/isa_traits.cc:
Define convert_and_round function here
arch/mips/isa_traits.hh:
Use "enums" to define FP conversion types & Round Modes
Declare convert_and_round function here
--HG--
extra : convert_revision : 0f4f8c1732a53b277361559ea71af2a1feb4fc64
130 lines
4.6 KiB
C++
130 lines
4.6 KiB
C++
// -*- mode:c++ -*-
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let {{
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def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
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postacc_code = '', base_class = 'Memory',
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decode_template = BasicDecode, exec_template_base = ''):
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# Make sure flags are in lists (convert to lists if not).
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mem_flags = makeList(mem_flags)
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inst_flags = makeList(inst_flags)
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# add hook to get effective addresses into execution trace output.
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ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
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# generate code block objects
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ea_cblk = CodeBlock(ea_code)
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memacc_cblk = CodeBlock(memacc_code)
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postacc_cblk = CodeBlock(postacc_code)
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# Some CPU models execute the memory operation as an atomic unit,
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# while others want to separate them into an effective address
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# computation and a memory access operation. As a result, we need
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# to generate three StaticInst objects. Note that the latter two
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# are nested inside the larger "atomic" one.
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# generate InstObjParams for EAComp object
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ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags)
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# generate InstObjParams for MemAcc object
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memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags)
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# in the split execution model, the MemAcc portion is responsible
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# for the post-access code.
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memacc_iop.postacc_code = postacc_cblk.code
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# generate InstObjParams for InitiateAcc, CompleteAcc object
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# The code used depends on the template being used
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if (exec_template_base == 'Load'):
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initiateacc_cblk = CodeBlock(ea_code + memacc_code)
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completeacc_cblk = CodeBlock(memacc_code + postacc_code)
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elif (exec_template_base == 'Store'):
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initiateacc_cblk = CodeBlock(ea_code + memacc_code)
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completeacc_cblk = CodeBlock(postacc_code)
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else:
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initiateacc_cblk = ''
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completeacc_cblk = ''
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initiateacc_iop = InstObjParams(name, Name, base_class, initiateacc_cblk,
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inst_flags)
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completeacc_iop = InstObjParams(name, Name, base_class, completeacc_cblk,
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inst_flags)
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if (exec_template_base == 'Load'):
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initiateacc_iop.ea_code = ea_cblk.code
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initiateacc_iop.memacc_code = memacc_cblk.code
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completeacc_iop.memacc_code = memacc_cblk.code
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completeacc_iop.postacc_code = postacc_cblk.code
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elif (exec_template_base == 'Store'):
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initiateacc_iop.ea_code = ea_cblk.code
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initiateacc_iop.memacc_code = memacc_cblk.code
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completeacc_iop.postacc_code = postacc_cblk.code
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# generate InstObjParams for unified execution
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cblk = CodeBlock(ea_code + memacc_code + postacc_code)
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iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
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iop.ea_constructor = ea_cblk.constructor
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iop.ea_code = ea_cblk.code
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iop.memacc_constructor = memacc_cblk.constructor
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iop.memacc_code = memacc_cblk.code
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iop.postacc_code = postacc_cblk.code
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if mem_flags:
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s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
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iop.constructor += s
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memacc_iop.constructor += s
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# select templates
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memAccExecTemplate = eval(exec_template_base + 'MemAccExecute')
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fullExecTemplate = eval(exec_template_base + 'Execute')
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initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
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completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
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# (header_output, decoder_output, decode_block, exec_output)
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return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop),
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decode_template.subst(iop),
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EACompExecute.subst(ea_iop)
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+ memAccExecTemplate.subst(memacc_iop)
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+ fullExecTemplate.subst(iop)
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+ initiateAccTemplate.subst(initiateacc_iop)
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+ completeAccTemplate.subst(completeacc_iop))
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}};
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output exec {{
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using namespace MipsISA;
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/// CLEAR ALL CPU INST/EXE HAZARDS
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inline void
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clear_exe_inst_hazards()
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{
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//CODE HERE
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}
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/// Check "FP enabled" machine status bit. Called when executing any FP
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/// instruction in full-system mode.
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/// @retval Full-system mode: NoFault if FP is enabled, FenFault
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/// if not. Non-full-system mode: always returns NoFault.
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#if FULL_SYSTEM
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inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
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{
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Fault fault = NoFault; // dummy... this ipr access should not fault
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if (!Mips34k::ICSR_FPE(xc->readIpr(MipsISA::IPR_ICSR, fault))) {
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fault = FloatEnableFault;
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}
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return fault;
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}
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#else
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inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
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{
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return NoFault;
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}
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#endif
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}};
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