arch/alpha/alpha_linux_process.cc: Added using directive for AlphaISA namespace arch/alpha/alpha_memory.hh: arch/alpha/isa/branch.isa: cpu/pc_event.hh: Added typedefs for Addr arch/alpha/alpha_tru64_process.cc: arch/alpha/arguments.cc: Added using directive for AlphaISA arch/alpha/ev5.hh: Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace. arch/alpha/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/alpha/isa/main.isa: Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh arch/alpha/isa/mem.isa: Untemplatized StaticInst and StaticInstPtr arch/alpha/isa/pal.isa: cpu/base_dyn_inst.cc: Untemplatized StaticInstPtr arch/alpha/isa_traits.hh: Changed variables to be externs instead of static since they are part of a namespace and not a class. arch/alpha/stacktrace.cc: Untemplatized StaticInstPtr, and added a using directive for AlphaISA. arch/alpha/stacktrace.hh: Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr arch/alpha/vtophys.cc: Added a using directive for AlphaISA arch/alpha/vtophys.hh: Added the AlphaISA namespace specifier where needed arch/isa_parser.py: Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace. base/loader/object_file.hh: cpu/o3/bpred_unit.hh: Added a typedef for Addr base/loader/symtab.hh: Added a typedef for Addr, and added a TheISA to Addr in another typedef base/remote_gdb.cc: Added a using namespace TheISA, and untemplatized StaticInstPtr base/remote_gdb.hh: Added typedefs for Addr and MachInst cpu/base.cc: Added TheISA specifier to some variables exported from the isa. cpu/base.hh: Added a typedef for Addr, and TheISA to some variables from the ISA cpu/base_dyn_inst.hh: Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA. cpu/exec_context.hh: Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa cpu/exetrace.hh: Added typedefs for some types from the ISA, and untemplatized StaticInstPtr cpu/memtest/memtest.cc: cpu/o3/btb.cc: dev/baddev.cc: dev/ide_ctrl.cc: dev/ide_disk.cc: dev/isa_fake.cc: dev/ns_gige.cc: dev/pciconfigall.cc: dev/platform.cc: dev/sinic.cc: dev/uart8250.cc: kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: kern/system_events.cc: kern/tru64/dump_mbuf.cc: kern/tru64/tru64_events.cc: sim/process.cc: sim/pseudo_inst.cc: sim/system.cc: Added using namespace TheISA cpu/memtest/memtest.hh: cpu/trace/opt_cpu.hh: cpu/trace/reader/itx_reader.hh: dev/ide_disk.hh: dev/pcidev.hh: dev/platform.hh: dev/tsunami.hh: sim/system.hh: sim/vptr.hh: Added typedef for Addr cpu/o3/2bit_local_pred.hh: Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr cpu/o3/alpha_cpu.hh: Added typedefs for Addr and IntReg cpu/o3/alpha_cpu_impl.hh: Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed. cpu/o3/alpha_dyn_inst.hh: Cleaned up some typedefs, and untemplatized StaticInst cpu/o3/alpha_dyn_inst_impl.hh: untemplatized StaticInstPtr cpu/o3/alpha_impl.hh: Fixed up a typedef of MachInst cpu/o3/bpred_unit_impl.hh: Added a using TheISA::MachInst to a function cpu/o3/btb.hh: Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr cpu/o3/commit.hh: Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now. cpu/o3/cpu.cc: Cleaned up namespace issues cpu/o3/cpu.hh: Cleaned up namespace usage cpu/o3/decode.hh: Removed typedef of ISA, and changed it to TheISA cpu/o3/fetch.hh: Fized up typedefs, and changed ISA to TheISA cpu/o3/free_list.hh: Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh cpu/o3/iew.hh: Removed typedef of ISA cpu/o3/iew_impl.hh: Added TheISA namespace specifier to MachInst cpu/o3/ras.hh: Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr. cpu/o3/regfile.hh: Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile cpu/o3/rename.hh: Changed ISA to TheISA, and added a typedef for RegIndex cpu/o3/rename_map.hh: Added an include for arch/isa_traits.hh, and a typedef for RegIndex cpu/o3/rob.hh: Added a typedef for RegIndex cpu/o3/store_set.hh: cpu/o3/tournament_pred.hh: Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr cpu/ozone/cpu.hh: Changed ISA into TheISA, and untemplatized StaticInst cpu/pc_event.cc: Added namespace specifier TheISA to Addr types cpu/profile.hh: kern/kernel_stats.hh: Added typedef for Addr, and untemplatized StaticInstPtr cpu/simple/cpu.cc: Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst cpu/simple/cpu.hh: Added a typedef for MachInst, and untemplatized StaticInst cpu/static_inst.cc: Untemplatized StaticInst cpu/static_inst.hh: Untemplatized StaticInst by using the TheISA namespace dev/alpha_console.cc: Added using namespace AlphaISA dev/simple_disk.hh: Added typedef for Addr and fixed up some formatting dev/sinicreg.hh: Added TheISA namespace specifier where needed dev/tsunami.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Added using namespace TheISA. It might be better for it to be AlphaISA dev/tsunami_cchip.cc: Added typedef for TheISA. It might be better for it to be AlphaISA kern/linux/aligned.hh: sim/pseudo_inst.hh: Added TheISA namespace specifier to Addr kern/linux/linux_threadinfo.hh: Added typedef for Addr, and TheISA namespace specifier to StackPointerReg kern/tru64/mbuf.hh: Added TheISA to Addr type in structs sim/process.hh: Added typedefs of Addr, RegFile, and MachInst sim/syscall_emul.cc: Added using namespace TheISA, and a cast of VMPageSize to the int type sim/syscall_emul.hh: Added typecast for Addr, and TheISA namespace specifier for where needed --HG-- extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
225 lines
6.2 KiB
C++
225 lines
6.2 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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* Declaration of a memory trace CPU object for optimal caches. Uses a memory
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* trace to access a fully associative cache with optimal replacement.
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*/
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#ifndef __CPU_TRACE_OPT_CPU_HH__
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#define __CPU_TRACE_OPT_CPU_HH__
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#include <vector>
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#include "mem/mem_req.hh" // for MemReqPtr
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#include "sim/eventq.hh" // for Event
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#include "sim/sim_object.hh"
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// Forward Declaration
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class MemTraceReader;
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/**
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* A CPU object to simulate a fully-associative cache with optimal replacement.
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*/
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class OptCPU : public SimObject
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{
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protected:
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typedef TheISA::Addr Addr;
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private:
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typedef int RefIndex;
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typedef std::vector<RefIndex> L3Table;
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typedef std::vector<L3Table> L2Table;
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typedef std::vector<L2Table> L1Table;
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/**
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* Event to call OptCPU::tick
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*/
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class TickEvent : public Event
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{
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private:
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/** The associated CPU */
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OptCPU *cpu;
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public:
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/**
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* Construct this event;
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*/
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TickEvent(OptCPU *c);
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/**
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* Call the tick function.
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*/
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void process();
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/**
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* Return a string description of this event.
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*/
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const char *description();
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};
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TickEvent tickEvent;
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class RefInfo
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{
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public:
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RefIndex nextRefTime;
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Addr addr;
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};
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/** Reference Information, per set. */
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std::vector<std::vector<RefInfo> > refInfo;
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/** Lookup table to track blocks in the cache heap */
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L1Table lookupTable;
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/**
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* Return the correct value in the lookup table.
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*/
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RefIndex lookupValue(Addr addr)
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{
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int l1_index = (addr >> 32) & 0x0f;
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int l2_index = (addr >> 16) & 0xffff;
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int l3_index = addr & 0xffff;
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assert(l1_index == addr >> 32);
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return lookupTable[l1_index][l2_index][l3_index];
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}
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/**
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* Set the value in the lookup table.
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*/
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void setValue(Addr addr, RefIndex index)
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{
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int l1_index = (addr >> 32) & 0x0f;
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int l2_index = (addr >> 16) & 0xffff;
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int l3_index = addr & 0xffff;
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assert(l1_index == addr >> 32);
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lookupTable[l1_index][l2_index][l3_index]=index;
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}
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/**
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* Initialize the lookup table to the given value.
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*/
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void initTable(Addr addr, RefIndex index);
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void heapSwap(int set, int a, int b) {
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RefIndex tmp = cacheHeap[a];
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cacheHeap[a] = cacheHeap[b];
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cacheHeap[b] = tmp;
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setValue(refInfo[set][cacheHeap[a]].addr, a);
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setValue(refInfo[set][cacheHeap[b]].addr, b);
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}
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int heapLeft(int index) { return index + index + 1; }
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int heapRight(int index) { return index + index + 2; }
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int heapParent(int index) { return (index - 1) >> 1; }
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RefIndex heapRank(int set, int index) {
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return refInfo[set][cacheHeap[index]].nextRefTime;
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}
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void heapify(int set, int start){
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int left = heapLeft(start);
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int right = heapRight(start);
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int max = start;
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if (left < assoc && heapRank(set, left) > heapRank(set, start)) {
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max = left;
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}
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if (right < assoc && heapRank(set, right) > heapRank(set, max)) {
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max = right;
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}
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if (max != start) {
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heapSwap(set, start, max);
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heapify(set, max);
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}
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}
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void verifyHeap(int set, int start) {
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int left = heapLeft(start);
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int right = heapRight(start);
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if (left < assoc) {
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assert(heapRank(set, start) >= heapRank(set, left));
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verifyHeap(set, left);
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}
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if (right < assoc) {
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assert(heapRank(set, start) >= heapRank(set, right));
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verifyHeap(set, right);
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}
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}
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void processRankIncrease(int set, int start) {
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int parent = heapParent(start);
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while (start > 0 && heapRank(set,parent) < heapRank(set,start)) {
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heapSwap(set, parent, start);
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start = parent;
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parent = heapParent(start);
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}
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}
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void processSet(int set);
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static const RefIndex InfiniteRef = 0x7fffffff;
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/** Memory reference trace. */
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MemTraceReader *trace;
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/** Cache heap for replacement. */
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std::vector<RefIndex> cacheHeap;
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/** The number of blocks in the cache. */
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const int numBlks;
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const int assoc;
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const int numSets;
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const int setMask;
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int misses;
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int hits;
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public:
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/**
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* Construct a OptCPU object.
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*/
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OptCPU(const std::string &name,
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MemTraceReader *_trace,
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int block_size,
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int cache_size,
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int assoc);
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/**
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* Perform the optimal replacement simulation.
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*/
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void tick();
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};
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#endif // __CPU_TRACE_OPT_CPU_HH__
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